Micron Technology Incorporated

Thomas Fiala

Nagendra Prasad Ganesh Rao

Sead Zildzic, Jr

Paing Z Htet

Zhenming Zhou

Jian Huang

A memory device includes a memory array having a plurality of wordlines coupled with respective memory cells of the memory array. Control logic is operatively coupled with the memory array, the control logic to perform operations including: determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed; adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.

Partial block read level voltage compensation to decrease read trigger rates

A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.

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Folsom, CA, United States of America

Thomas Fiala