Imagination Technologies Limited

Thomas Ferrere

Sam Elliott

Faizan Nazar

Simon Gaulter

Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

Method and system for verifying a sorter

A method and system for processing a set of 'k' floating point numbers to perform addition and/or subtraction is disclosed. Each floating-point number comprises a mantissa (m) and an exponent (e). The method comprises receiving the set of ‘k’ floating point numbers in a first format, each floating-point number in the first format comprising a mantissa (m) with a bit-length of ‘b’ bits. The method further comprises creating a set of ‘k’ numbers (y) based on the mantissas of the ‘k’ floating-point numbers, the numbers having a bit-length of ‘n’ bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit length ‘b’ of the mantissa (m). The method includes identifying a maximum exponent (e) among the exponents e, aligning the magnitude bits of the numbers (y) based on the maximum exponent (e) and processing the set of ‘k’ numbers concurrently.

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Hertfordshire, United Kingdom

Thomas Ferrere