Intel Corporation

Thomas F Raoux

Michael Apodaca

Kai Xiao

Carson Brownlee

Joshua D Barczak

Carsten Benthin

Gabor Liktor

Karthik Vaidyanathan

John G Gierach

Prasoonkumar Surti

Travis T Schluessler

David M Cimini

Joshua Barczak

Satyajit Sarangi

Guei-Yuan Lueh

John H Feit

Konstantin Levit-Gurevich

Subramaniam M Maiyuran

Jon N Hasselgren

Abhishek Venkatesh

James A Valerio

Devan Burke

Sven Woop

Philip R Laws

Saurabh Sharma

Peng Guo

Rahul P Sathe

Aleksander Olek Neyman

Somnath Ghosh

Won-Jong Lee

Pawel Majewski

Hashem Hashemi

Srividya Karumuri

Uddipan Mukherjee

Debraj Bose

Sthiti Deka

Yohai Gevim

Abhishek Ventakesh

Rama S B Harihara

Wojtek Rajski

Jeremy Brennan

Bartosz Spitzbarth

An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

Apparatus and method for ray tracing instruction processing and execution

Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.

Context-aware compression with quantization of hierarchical transform matrices

Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.

Early termination in bottom-up acceleration data structure refit

Examples are described here that can be used to enable a main routine to request subroutines or other related code to be executed with other instantiations of the same subroutine or other related code for parallel execution. A sorting unit can be used to accumulate requests to execute instantiations of the subroutine. The sorting unit can request execution of a number of multiple instantiations of the subroutine corresponding to a number of lanes in a SIMD unit. A call stack can be used to share information to be accessed by a main routine after execution of the subroutine completes.

Techniques to manage execution of divergent shaders

Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.

Real time ray tracing (RTRT)-based adaptive multi-frequency shading (AMFS)

An apparatus to facilitate an update of shader data constants. The apparatus includes one or more processors to detect a change to one or more data constants in a shader program, generate a micro-code block including updated constants data during execution of the shader program and transmit the micro-code block to the shader program.

Dynamic constant update mechanism

Cloud-based real time rendering. For example, one embodiment of a system comprises: a first graphics processing node to perform a first set of graphics processing operations to render a graphics scene, the first set of graphics processing operations comprising ray-tracing independent operations; an interconnect or network interface coupling the first graphics processing node to a second graphics processing node; the second graphics processing node to receive an indication of a current view of a user of the first graphics processing node and to receive or construct a view-independent surface generated by view-independent ray traversal and intersection operations; the second graphics processing node to responsively perform a view-dependent translation of the view-independent surface based on the current view of the user to generate a view-dependent surface and to provide the view-dependent surface to the first graphics processing node; and the first graphics processing node to perform a second set of graphics processing operations to complete rendering of the graphics scene using the view-dependent surface.

Cloud-based realtime raytracing

Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

Programmable ray tracing with hardware acceleration on a graphics processor

A mechanism is described for facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance on computing devices. A method of embodiments, as described herein, includes detecting a command stream associated with an application, where the command stream includes dispatches. The method may further include evaluating processing parameters relating to each of the dispatches, where evaluating further includes associating a first plan with one or more of the dispatches to transform the command stream into a transformed command stream. The method may further include associating, based on the first plan, a second plan to the one or more of the dispatches, where the second plan represents the transformed command stream. The method may further include executing the second plan, where execution of the second plan includes processing the transformed command stream in lieu of the command stream.

Facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance at computing devices

Growing community of inventors

Mountain View, CA, United States of America

Thomas F Raoux