Motorola Corporation

Freescale Semiconductor,inc.

Thomas F McNelly

Bich-Yen Nguyen

Philip J Tobin

James D Hayden

Howard C Kirsch

Ertugrul Demircan

Yasunobu Kosa

Frank Kelsey Baker, Jr

Frank K Baker

A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions.

Inductive element with interrupter region and method for forming

Inductive element with interrupter region

A static-random-access memory cell comprising floating node capacitors is disclosed. In one embodiment, the storage nodes acts as the first plates for the floating node capacitors, and a conductive member acts as the second plates for the floating node capacitors. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cell. In another embodiment, a conductive member acts as the second plates of a plurality of memory cells. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cells. Processes for forming the memory cells is also disclosed.

Semiconductor device having a static-random-access memory cell

An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).

Thin film transistor and method of formation

Process for forming a static-random-access memory cell

Method for forming a thin film transistor

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Austin, TX, United States of America

Thomas F McNelly