Honeywell Information Systems Inc.

Bull Hn Information Systems, Inc.

Honeywell Bull, Inc.

Nec Corporation

Zenith Data Systems Corporation

Packard Bell Nec

Bull Nh Information Systems, Inc.

Ming-tzer Miu

Thomas F. Joyce

Richard P. Kelly

Ming T. Miu

Thomas F Joyce

Jian-Kuo Shen

Richard P Kelly

Bruno DiPlacido, Jr

Chester M Nibby, Jr

Jeffrey S Somers

Thomas L Murray, Jr

James F Bertone

Michelle A Pence

G Lewis Steiner

Marc Sanfacon

Martin Massucci

Thomas O Holtey

James W Keeley

Richard P Brown

Michel M Raguin

Lance J McNally

Richard A Lemay

Ming T Miu

William Panepinto, Jr

Forrest M Phillips

William E Woods

William S Wu

Suresh K Marisetty

Puthiya K Nizar

Norman J Rasmussen

Robert C Miller

Eugene Nusinov

Steven S Smith

George J Barlow

Virendra S Negi

Arthur Peters

David E Cushing

Gary J Goss

Arnold J Smith

Amy E Gilfeather

Marc C Vogt

Lance T McNally

Martin M Massucci

Robert V Ledoux, Deceased

Lewis G Steiner

Bruno Diplacido

Lance Mcnally

The invention is directed to a memory controller for use with memory having varying timing characteristics. In particular, the timing characteristics of the various memory devices are determined and used to generate timing signals commensurate with each particular memory device.

Symmetric multiprocessing system with unified environment and distributed system functions

A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

Symmetric multiprocessing system with unified environment and

Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a memory operation and wherein the second timing control value represents information representing other timing events. That is, the state machine of the present invention requires a distinct starting control value, separate from other timing values, for calculation of appropriate memory access parameters.

Adaptively generating timing signals for access to various memory

The emulator includes first and second pipelined stages connected through a bidirectional bus for executing source instructions normally executed by a different/source computer in a highly overlapped manner. The first stage includes an emulator chip which performs the function of fetching and decoding each source instruction stored in cache memory resulting in the generation of a number of vector addresses required for executing the instruction by the second stage. The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and data fetched during subroutine execution. In pipelined fashion, the emulator chip fetches and decodes each source instruction which generates a vector branch address which is loaded into the branch vector register while the microprocessor chip fetches and executes emulation subroutines specified by the vector address transferred via the bus for each previously decoded source instruction.

Emulation of CISC instructions by RISC instructions using two pipelined

A processing unit tightly couples to a system bus which utilizes a split cycle bus protocol and includes a local memory which is accessible from such bus. The local memory couples to a high speed synchronous bus which operates according to a predetermined bus protocol. The processing unit includes a state machine which couples to the high speed synchronous bus and to the asynchronous system bus. The state machine emulates the predetermined bus synchronous protocol in transferring commands issued to the local memory from the system bus which uses the split cycle protocol.

Bus controller having state machine for translating commands and

A processing unit tightly couples to a system bus and includes a local memory which is accessible from such bus. The processing unit includes a high performance microprocessor which tightly couples to the local memory through a high speed synchronous bus shared with a plurality of synchronous state machines. A microprocessor internal bus state machine and the plurality of state machines control local bus accesses for transferring commands generated by the microprocessor and commands transferred from the system bus under the control of an external state machine for execution by a local memory state machine and the processor state machine, respectively, which also couples to the system bus.

Processing unit having multiple synchronous bus for sharing access and

A system includes first and second processing units which are interconnected by a bidirectional bus. The first processing unit is a microprocessor chip programmed for executing procedures stored in an on-chip instruction cache unit. The second processing unit receives requests from an external source such as a system bus. The microprocessor chip includes a branch vector facility which connects to the bus. The second processing unit in response to an external request, generates a vector branch address. The processing unit transfers the vector branch address to the branch vector facility for storage along with setting a write indicator. The microprocessor chip, upon detecting that the write indicator was set, branches to the procedure specified by the branch vector address for executing the instructions of the procedure to carry out those operations required for processing the external request or event.

External procedure invocation apparatus utilizing internal branch vector

A multiprocessor system includes a number of system processors which tightly couple to a system bus to share a main or system memory and a number of on-board memory processors which also are tightly coupled to the system bus. Each processor has a high performance microprocessor which tightly couples to an on-board or local memory through the microprocessor's local bus. System memory is accessible using a memory lock protocol while the local memory is accessible through a bus lock protocol. Each on-board memory processor includes a lock mechanism which enables the processing of memory lock commands directed to its local memory received via the system bus from any other processor and for issuing memory lock commands to system memory.

Method and apparatus for avoiding processor deadly embrace in a

The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the sytem bus.

Recovery method and apparatus for a pipelined processing unit of a

In a data processing system having a plurality of tightly coupled data processing units connected by an asynchronous system bus, apparatus and an associated method are described for maintaining the coherency of data groups stored in instruction cache units and execution cache units. The apparatus includes a monitor unit as part of the bus interface unit, and a bus interface unit coupling each associated data processing unit to the system bus. The monitor unit receives signals, applied to the system bus, identifying data groups transferred between the memory unit and the data processing units, including those data groups originating from the bus interface unit of which the monitor unit is a component. The bus interface unit includes directories duplicating the contents of the instruction cache unit directory and the execution cache unit directory. The monitor unit, in response to signals applied to the system bus, identifies operations that can compromise the integrity of signals stored in the associated data processing unit. The monitor unit accesses the appropriate duplicate directory to determine if the address of a compromised data group validly exists in the duplicate directory. When an address is stored in the duplicate directory along with a valid signal, the valid signal is removed from both the cache directory and the duplicate directory.

Apparatus and method for data group coherency in a tightly coupled data

In a data processing system using a virtual memory adressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value.

Method for reexecuting instruction by altering high bits of instruction

In a data processing system in which each of the data processing units is implemented using pipeline techniques and has a cache memory unit employing a store through strategy, the time required to prepare a write instruction operand address can be substantially shorter than the time required by the execution unit to prepare the associated write instruction operand. In order to utilize the time difference, apparatus is included in the execution cache unit for storing the write instruction operand address during the preparation of the associated write instruction operand. After storing the write instruction operand address, a next address is entered in an input register of the execution cache unit. When the newly entered address is associated with a read instruction, does not conflict with the write instruction operand address, and produces a 'hit' signal when applied to the execution cache unit tag directory, the read instruction is processed by the execution unit. When a second write instruction operand address is entered in the input register, the read instruction operand address conflicts with the stored write instruction operand address or the read instruction operand address results in a 'miss' when applied to the execution cache tag directory unit, the address is stored in the input register until the write instruction operand has been determined and the associated write instruction has been procossed by the execution cache unit.

Apparatus and method for simultaneous execution of a write instruction

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Westford, MA, United States of America

Thomas F Joyce