Globalfoundries U.S. Inc.

International Business Machines Corporation

Globalfoundries Inc.

Thomas F Houghton

Yusheng Bian

Asli Sahin

Karen A Nummy

Nicholas A Polomoff

Richard Paul Volant

Yun-Yu Wang

Zhuojie Wu

Nitin H Parbhoo

Jennifer A Oakley

Jeremy S Alderman

Mukta G Farooq

Ajey Poovannummoottil Jacob

Keith Kwong Hon Wong

Robert K Leidy

Richard Anthony Conti

Emily R Kinser

Michael F Lofaro

Kenneth John Giewont

Darryl D Restaino

Daewon Yang

Bo Peng

Kevin K Dezfulian

Chester T Dziobkowski

Koushik Ramachandran

Tymon Barwicz

Jeffery Burton Maxson

Ann H McDonald

Ian Melville

Paul N Chaloux, Jr

Pallabi Das

Gregory Bazan

Mutka G Farooq

Richard K West

A photonic integrated circuit (PIC) die are provided. The PIC die includes a set of optical connect grooves including a first groove aligning a core of a first optical fiber positioned with a first optical component in a first layer at a first vertical depth in a plurality of layers of a body of the die, and a second groove aligning a core of a second optical fiber positioned therein with a second optical component in a second, different layer at a second different vertical depth in the plurality of layers. The grooves may also have end faces at different lateral depths from an edge of the body of the PIC die. Any number of the first and second grooves can be used to communicate an optical signal to any number of layers at different vertical and/or lateral depths within the body of the PIC die.

PIC die and package with multiple level and multiple depth connections of fibers to on-chip optical components

Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes a waveguide core region on a first dielectric layer, and a second dielectric layer on the waveguide core region and the first dielectric layer. The waveguide core region has a tapered section with an end surface that terminates adjacent to an edge of the first dielectric layer. The second dielectric layer includes a first trench and a second trench that are each positioned adjacent to the tapered section of the waveguide core region.

Edge couplers including a grooved membrane

Structures for a cavity included in a photonics chip and methods of fabricating a structure for a cavity included in a photonics chip. The structure includes a substrate, a back-end-of-line stack having interlayer dielectric layers on the substrate, and a cavity penetrating through the back-end-of-line stack and into the substrate. The cavity includes first sidewalls and second sidewalls, and the second sidewalls have an alternating arrangement with the first sidewalls to define non-right-angle corners.

Photonics chips including cavities with non-right-angle internal corners

The present disclosure relates to semiconductor structures and, more particularly, to a moisture seal for photonic devices and methods of manufacture. The structure includes: a first trench in at least one substrate material; a guard ring structure with an opening and which at least partially surrounds the first trench; and a second trench at a dicing edge of the substrate, the second trench being lined on sidewalls with barrier material and spacer material over the barrier material.

Moisture seal for photonic devices

PIC die packages may include a PIC die including: a body having a plurality of layers including a plurality of interconnect layers. A first optical fiber is positioned in a groove and a second optical fiber positioned in another groove in the edge of the body. The first optical fiber is aligned with an optical component in a first layer of the body at a first vertical depth, and the second optical fiber is aligned with another optical component in a second, different layer of the body at a second different vertical depth. A cover is over at least a portion of the body. The cover includes a member having a face defining a first seat therein having a first height to receive a portion of the first optical fiber, and defining a second seat therein having a second, different height to receive a portion of the second optical fiber.

PIC die and package with cover for multiple level and multiple depth connections of fibers to on-chip optical components

A photonics integrated circuit includes a semiconductor substrate; a buried insulator layer positioned over the semiconductor substrate; and a back-end-of-line (BEOL) insulator stack over a first portion of the buried insulator layer. In addition, the PIC includes a silicon nitride (SiN) waveguide edge coupler positioned in a first region over the buried insulator layer and at least partially under the BEOL insulator stack. An oxide layer extends over a side of the BEOL insulator stack. The SiN waveguide edge coupler provides better power handling and fabrication tolerance than silicon waveguide edge couplers, despite the location under various BEOL layers. The PIC can also include silicon waveguide edger coupler(s).

Photonics integrated circuit with silicon nitride waveguide edge coupler

Structures for an edge coupler and methods of fabricating a structure for an edge coupler. A waveguide core and a coupler are formed over a layer stack that includes a first dielectric layer and a second dielectric layer over the first dielectric layer. The coupler includes a first plurality of grating structures and a transition structure including a second plurality of grating structures that are positioned between the first plurality of grating structures and the waveguide core. The first plurality of grating structures include respective widths that vary as a function of position relative to the transition structure.

Edge couplers for photonics applications

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of creating a non-permeable edge seal around a whole wafer. The edge seal may be located between an inner region of a wafer comprising product chips and an outer edge of the wafer. The edge seal may comprise a fillet region adjacent the inner region, and a dielectric extension adjacent the fillet region. The dielectric extension region may be impermeable to moisture and composed of a dielectric layer on the wafer and a capping layer on the dielectric layer. The fillet region may comprise a lower metal fillet directly on the wafer, a dielectric layer on the lower metal fillet, an upper metal fillet on the dielectric layer, and a capping layer on the upper metal fillet. The fillet region may be adjacent to and in contact with a permeable layer formed on the product region.

Whole wafer edge seal

A layer of polymer material is applied on a peripheral region of at least one of the two substrates to be bonded prior to bonding. The bonded structure formed thereby includes a first substrate, a second substrate in direct contact with the first substrate, and a ring of the polymer material in direct contact with the first substrate at a first interface and in direct contact with the second substrate. The ring of polymer material laterally surrounds and seals the interface at which the first substrate contacts the second substrate. A ring-shaped cavity can be formed within the polymeric ring. Alternately, the first interface and the second interface can be contiguous without a ring-shaped cavity between the first and second substrates.

Polymeric edge seal for bonded substrates

A method of forming a TEOS oxide layer over an nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer formed on a substrate. The method includes forming the nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer on a top surface and a top side beveled edge proximate to the top surface of a substrate; removing or preventing formation of a carbon-rich layer on a bottom side bevel edge region proximate to a bottom surface of the substrate or converting the carbon-rich layer to nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide; and forming the TEOS oxide layer on the top surface, the top side beveled edge and the bottom side bevel edge region of the substrate.

Method for preventing backside defects in dielectric layers formed on semiconductor substrates

The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.

Bilayer cap structure including HDP/bHDP films for conductive metallization and method of making same

A method for simultaneously forming a level of interconnection metallurgy over, and inter-level via studs through, an insulating layer of a semiconductor chip. The method comprises the steps of forming a plurality of via holes in the insulating layer, high-mobility sputtering conductive material on to the surface of the insulating layer and into the via holes therein, masking the conductive material layer, and then ion beam milling through the mask to form a patterned interconnection layer. The high-mobility sputtering step is accomplished by reducing the background pressure to below 10.sup.-7 Torr to eliminate non-mobile species, maintaining a sputter pressure of less than 7 microns, maintaining an appropriate chip bias level to keep the conductive material molecules mobile until they reach their lowest energy state, and maintaining the temperature of the chip at a level so that a high sputter species mobility is maintained. This high-mobility sputtering forms a substantially planar conductive layer and fills the via holes without void formation. The foregoing process permits extremely dense interconnection levels, is especially suited for multiple interconnection level designs, and is extendable to large diameter wafer fabrication.

Method for simultaneously forming an interconnection level and via studs

Growing community of inventors

Hopewell Junction, NY, United States of America

Thomas F Houghton