Texas Instruments Corporation

Thomas Eugene Grebs

Osvaldo Jorge Lopez

Simon John Molloy

Jonathan Almeria Noquil

Walter Hans Paul Schroen

Christopher Boguslaw Kocon

Touhidur Rahman

Seetharaman Sridhar

Hong Yang

Sunglyong Kim

Ya Ping Chen

An integrated circuit includes a trench gate MOSFET including MOSFET cells. Each MOSFET cell includes an active trench gate in an n-epitaxial layer oriented in a first direction with a polysilicon gate over a lower polysilicon portion. P-type body regions are between trench gates and are separated by an n-epitaxial region. N-type source regions are located over the p-type regions. A gate dielectric layer is between the polysilicon gates and the body regions. A metal-containing layer contacts the n-epitaxial region to provide an anode of an embedded Schottky diode. A dielectric layer over the n-epitaxial layer has metal contacts therethrough connecting to the n-type source regions, to the p-type body regions, and to the anode of the Schottky diode.

Vertical trench gate MOSFET with integrated Schottky diode

A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

Photo-sensitive silicon package embedding self-powered electronic system

A self-powered electronic system comprises a first chip () of single-crystalline semiconductor embedded in a second chip () of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container () bordered by ridges (). The flat side () of the slab includes a heavily n-doped region () forming a pn-junction () with the p-type bulk. A metal-filled deep silicon via () through the p-type ridge () connects the n-region with the terminal () on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

A packaged electronic system comprises a slab () of low-grade silicon (l-g-Si) configured as ridges () framing a depression of depth () including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals () connected to attachment pads in the central area; and semiconductor chips () having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

Silicon package having electrical functionality by embedded passive components

An electronic system comprises a first chip of single-crystalline semiconductor shaped as a hexahedron and including a first electronic device embedded in a second chip of single-crystalline semiconductor shaped as a container having a slab bordered by retaining walls, and including a second electronic device. The container shaped as a slab bordered by the retaining walls and including conductive traces and terminals. The first chip is attached to the slab of second chip, forming nested chips. The first and second chips embedded in the container. The nested first and second chips are operable as an electronic system and the container is operable as the package of the system.

Silicon package for embedded electronic system having stacked semiconductor chips

A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

Trench MOSFET having reduced gate charge

An electronic system comprises a first chip () of single-crystalline semiconductor including a first electronic device embedded in a second chip () of single-crystalline semiconductor shaped as a container having a slab () bordered by ridges (), and including a second electronic device. The nested chips are assembled in a container of low-grade silicon shaped as a slabbordered by retaining wallsand including conductive traces and terminals. The first electronic device is connected to the second electronic device by attaching the first chip onto the slab of the second chip; and the first and second electronic devices are connected to the container by embedding the second chip in the container, wherein the nested first and second chips operate as an electronic system and the container operates as the package of the system. For first and second devices as field effect transistors, the system is a power block.

Growing community of inventors

Bethlehem, PA, United States of America

Thomas Eugene Grebs