Texas Instruments Corporation

Thomas Edward Lillibridge

Abbas Ali

David William Hamann

Richard Allen Faust

Kalyan Chakravarthy Cherukuri

Neil L Gardner

Srinivas Raghavan

A microelectronic device includes a deep trench test structure in semiconductor material of a substrate. The deep trench test structure has pad trench segments with a liner of electrically non-conductive material and a trench fill material on the liner, extending to tops of the pad trench segments. The pad trench segments extend across a probe pad region; at least 20 microns in every lateral direction. The trench fill material at the top of the pad trench segments occupies at least 25 percent of the probe pad region. The liner may electrically isolate the trench fill material from the semiconductor material, or the deep trench test structure may include a contact trench segment wherein the trench fill material contacts the semiconductor material. The deep trench test structure may be probed on the pad trench segments to measure an impedance between the trench fill material and the semiconductor material.

Electrical test structure and method for monitoring deep trench impedance to substrate

A method for fabricating conductive deep trenches in conjunction with shallow trench isolations in a semiconductor device. The disclosed method introduces an integrated sequence during which a shallow trench is etched and filled before a deep trench is etched and filled. The disclosed method advantageously reduces cone defects and process complexity associated with the formation of a conductive deep trench within a shallow trench isolation structure. Fabricated under the integrated sequence, the conductive deep trench may extend through a shallow trench dielectric layer and into the substrate, where the top surfaces of both the conductive deep trench and shallow trench dielectric layer are substantially cone free.

Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density

A semiconductor device with a deep trench has a dielectric liner formed on sidewalls and a bottom of the deep trench. A pre-etch deposition step of a two-step process forms a protective polymer on an existing top surface of the semiconductor device, and on the dielectric liner proximate to a top surface of the substrate. The pre-etch deposition step does not remove a significant amount of the dielectric liner from the bottom of the deep trench. A main etch step of the two-step process removes the dielectric liner at the bottom of the deep trench while maintaining the protective polymer at the top of the deep trench. The protective polymer is subsequently removed.

Substrate contact having substantially straight sidewalls to a top surface of the substrate

Substrate contact etch process

A method of fabricating metal-bearing structures in an integrated circuit such as metal-polysilicon capacitors using conductive metal compounds. Defects due to organometallic polymers formed during the etch of a hard mask material are minimized by using a process that includes a plasma etch for the hard mask that achieves a predominantly chemical character using a fluorine-based etch chemistry. Using a low-temperature liquid-phase strip of the hard mask photoresist instead of an ash prevents further cross-linking of polymers formed during the plasma etch. Etching the metal-bearing material using a hot fully-concentrated mixture of ammonium hydroxide and hydrogen peroxide allows short etch times that are particularly shortened for tantalum nitride films deposited with a nitrogen concentration of about 30 percent or greater.

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Plano, TX, United States of America

Thomas Edward Lillibridge