Sandia Corporation

The United States of America As Represented by the United States

The United States of America As Represented by the Department of Energy

Thomas E Zipperian

Gordon Cecil Osbourn

Stanley H Kravitz

Timothy J Drummond

Vincent Mark Hietala

Albert G Baca

Alan P Sylwester

Jon S Martens

Robert M Biefeld

Ian J Fritz

Andrew M Hecht

L Ralph Dawson

Tom Klitsner

Gail N Ryba

Todd Richard Christenson

David Samuel Ginley

Gregory A Vawter

Randy J Shul

Andrew A Allerman

David Ingersoll

Charles T Sullivan

Paul L Gourley

Antonio J Ricco

Robert C Hughes

Hong Q Hou

Chris P Tigges

Fred J Zutavern

Gert K Hohenwarter

Perry J Robertson

David S Ginley

Guillermo M Loubriel

Thomas A Plut

Steven R Kurtz

Alan Mar

Harold P Hjalmarson

Charles A Kelsey

Jay B Snelling

Paul S Peercy

Harry T Weaver

Roger J Chaffin

Wesley D Helgeson

Martin W O'Malley

Dennis D Huffman

Richard Lane

Ralph Dawson

Roger J Chaffin, Deceased

Darwin J Brown

Gary J Denison

Fuel cells and a novel membrane for use in fuel cells and manufacturing processes.

Fuel cell and membrane

An apparatus and method for fabricating a microbattery that uses silicon as the structural component, packaging component, and semiconductor to reduce the weight, size, and cost of thin film battery technology is described. When combined with advanced semiconductor packaging techniques, such a silicon-based microbattery enables the fabrication of autonomous, highly functional, integrated microsystems having broad applicability.

Apparatus and method for fabricating a microbattery

A photoconductive semiconductor switch with tailored doping profile zones beneath and extending laterally from the electrical contacts to the device. The zones are of sufficient depth and lateral extent to isolate the contacts from damage caused by the high current filaments that are created in the device when it is turned on. The zones may be formed by etching depressions into the substrate, then conducting epitaxial regrowth in the depressions with material of the desired doping profile. They may be formed by surface epitaxy. They may also be formed by deep diffusion processes. The zones act to reduce the energy density at the contacts by suppressing collective impact ionization and formation of filaments near the contact and by reducing current intensity at the contact through enhanced current spreading within the zones.

High gain photoconductive semiconductor switch having tailored doping profile zones

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary junction heterostructure field-effect transistor

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.

Superconducting flux flow digital circuits

A process for formulating non-hysteretic and hysteretic Josephson junctions using HTS materials which results in junctions having the ability to operate at high temperatures while maintaining high uniformity and quality. The non-hysteretic Josephson junction is formed by step-etching a LaAlO.sub.3 crystal substrate and then depositing a thin film of TlCaBaCuO on the substrate, covering the step, and forming a grain boundary at the step and a subsequent Josephson junction. Once the non-hysteretic junction is formed the next step to form the hysteretic Josephson junction is to add capacitance to the system. In the current embodiment, this is accomplished by adding a thin dielectric layer, LaA1O.sub.3, followed by a cap layer of a normal metal where the cap layer is formed by first depositing a thin layer of titanium (Ti) followed by a layer of gold (Au). The dielectric layer and the normal metal cap are patterned to the desired geometry.

High temperature superconductor step-edge Josephson junctions using

A high gain photoconductive device for 8 to 12 .mu.m wavelength radiation including an active semiconductor region extending from a substrate to an exposed face, the region comprising a strained-layer superlattice of alternating layers of two different InAs.sub.1-x Sb.sub.x compounds having x&gt;0.75. A pair of spaced electrodes are provided on the exposed face, and changes in 8 to 12 .mu.m radiation on the exposed face cause a large photoconductive gain between the spaced electrodes.

Long wavelength, high gain InAsSb strained-layer superlattice

A layered semiconductor device with a nonvolatile three dimensional memory comprises a storage channel which stores charge carriers. Charge carriers flow laterally through the storage channel from a source to a drain. Isolation material, either a Schottky barrier or a heterojunction, located in a trench of an upper layer controllably retains the charge within the a storage portion determined by the confining means. The charge is retained for a time determined by the isolation materials' nonvolatile characteristics or until a change of voltage on the isolation material and the source and drain permit a read operation. Flow of charge through an underlying sense channel is affected by the presence of charge within the storage channel, thus the presences of charge in the memory can be easily detected.

Nonvolatile semiconductor memory having three dimension charge

In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated.

SLS complementary logic devices with increase carrier mobility

Methods of and apparatus for in vivo radiation measurements relay on a MOSFET dosimeter of high radiation sensitivity with operates in both the passive mode to provide an integrated dose detector and active mode to provide an irradiation rate detector. A compensating circuit with a matched unirradiated MOSFET is provided to operate at a current designed to eliminate temperature dependence of the device. Preferably, the MOSFET is rigidly mounted in the end of a miniature catheter and the catheter is implanted in the patient proximate the radiation source.

Methods of in vivo radiation measurement

A semiconductor high reflector comprising a number of thin alternating layers of semiconductor materials is electrically tunable and may be used as a temperature insensitive semiconductor laser in a Fabry-Perot configuration.

Semiconductor devices incorporating multilayer interference regions

During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In modular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substrate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating.

Substrate solder barriers for semiconductor epilayer growth

A field effect transistor comprises a semiconductor having a source, a drain, a channel and a gate in operational relationship. The semiconductor is a strained layer superlattice comprising alternating quantum well and barrier layers, the quantum well layers and barrier layers being selected from the group of layer pairs consisting of InGaAs/AlGaAs, InAs/InAlGaAs, and InAs/InAlAsP. The layer thicknesses of the quantum well and barrier layers are sufficiently thin that the alternating layers constitute a superlattice which has a superlattice conduction band energy level structure in k-vector space which includes a lowest energy .GAMMA.-valley and a next lowest energy L-valley, each k-vector corresponding to one of the orthogonal directions defined by the planes of said layers and the directions perpendicular thereto. The layer thicknesses of the quantum well layers are selected to provide a superlattice L.sub.2D -valley which has a shape which is substantially more two-dimensional than that of said bulk L-valley.

Field-effect transistor having a superlattice channel and high carrier

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Albuquerque, NM, United States of America

Thomas E Zipperian