Motorola Corporation

Freescale Semiconductor,inc.

Nxp USA, Inc.

Thomas E Wood

Henry G Hughes

Francine Y Robb

Colby Greg Rampley

F J Robinson

Frank T Laver

Bridget Svechovsky

An embodiment of a semiconductor wafer includes a semiconductor substrate, a plurality of through substrate vias (TSVs), and a conductive layer. The TSVs extend between first and second substrate surfaces. The TSVs include a first subset of trench via(s) each having a primary axis aligned in a first direction, and a second subset of trench via(s) each having a primary axis aligned in a second and different direction. The TSVs form an alignment pattern in an alignment area of the substrate. The conductive layer is directly connected to the second substrate surface and to first ends of the TSVs. Using the TSVs for alignment, the conductive layer may be patterned so that a portion of the conductive layer is directly coupled to the TSVs, and so that the conductive layer includes at least one conductive material void (e.g., in alignment with a passive component at the first substrate surface).

Semiconductor wafers with through substrate vias and back metal, and methods of fabrication thereof

A nano-scale tower structure array having increased surface area on each tower for gathering incident light is provided for use in three-dimensional solar cells. Embodiments enhance surface roughness of each tower structure to increase the surface area available for light gathering. Enhanced roughness can be provided by manipulating passivation layer etching parameters used during a formation process of the nano-scale tower structures, in order to affect surface roughness of a photoresist layer used for the etch. Manipulable etching parameters can include power, gas pressure, and etching compound chemistry.

Three-dimensional solar cell having increased efficiency

Filled trenches useful in semiconductor devices for isolation or other purposes are provided by etching a trench in the semiconductor substrate, lining the trench with a first material (e.g., silicon dioxide), covering the first material with a seed layer (e.g., polysilicon) for nucleating a further material, removing a part of the seed layer on the first material in an upper part of the trench, and then filling the trench by selectively depositing the further material (e.g., polysilicon) on the remaining seed layer. Thermally grown silicon dioxide is convenient for the first material. The first material and seed layer may extend over the substrate surface. The upper portion of the seed layer is conveniently removed by first covering the seed layer with a mask (e.g., photoresist) and then etching back the mask to expose the seed layer above the substrate surface and in the upper portion of the trench, leaving part of the mask in the lower portion of the trench. The exposed portion of the seed layer is then etched away. The remaining portion of the mask is removed before growing the trench filling material on the remaining part of the seed layer in the trench.

Method for filling trenches from a seed layer

Described is a process of utilizing carbon containing thick film spin-on glass with a directional etching process, such as RIE, or a downstream etching mechanism. As a layer of photoresist is etched from the surface of the spin-on glass, a skin layer of carbonless glass results. The skin layer protects the remaining glass from having the carbon removed allowing the use of spin-on glass on the order of 10,000 Angstroms thick.

Semiconductor processing utilizing carbon containing thick film spin-on

A spin-on glass consisting of, by volume: 1.0 parts tetraethoxysilane (TEOS, also known as tetraethylorthosilicate), methyltriethoxysilane, and dimethyldiethoxysilane in a 2/1/1 ratio; 1.1 parts ethanol (EtOH, also known as ethyl alcohol); 0.0002 parts hydrochloric acid (HCl); and 0.26 parts water (H.sub.2 O).

Spin-on glass for use in semiconductor processing

A method for processing multilevel interconnect lines separately from the multichip module on which they are to be employed. An oxide layer (16) is grown on a silicon wafer (14) and followed by a polyimide layer (18). Then a metal layer (20) is deposited and patterned. This is followed by another polyimide layer (24) having vias and another patterned metal layer (28). The vias allow for connections to be made between metal layers. Many polyimides and metal layers may be processed to allow for the desired number of levels of interconnect lines. After a last polyimide layer (32) is deposited, the oxide layer is etched to separate the multilevel interconnect line transfer (34) from the silicon wafer. After the processing of the multilevel interconnect lines, the multilevel interconnect line transfer is adhered to the multichip module in a predetermined relationship and electrical connections are made between them. In an alternative embodiment, a boron nitride layer (46) is bonded on a surface of silicon wafer (14). Stabilizing ring (44) is bonded on a second surface of the silicon wafer. Exposed regions of the wafer are etched away. The processing of multilevel interconnect line transfer (34) occurs on boron nitride layer (46) in the same manner as previously described.

Growing community of inventors

Chandler, AZ, United States of America

Thomas E Wood