Freescale Semiconductor,inc.

Motorola Corporation

Nxp B.v.

Nxp Usa, Inc.

Freescale Semiconductors Inc.

Thomas E Tkacik

Lawrence Loren Case

Carlin R Covey

David H Hartley

Matthew W Brocker

Rodney D Ziolkowski

Kayhan Kucukcakar

Mark D Redman

Douglas Allan Hardy

Steven D Millman

Asaf Ashkenazi

Steven R Tugenberg

David G Abdoo

Rajesh Gupta

Chih-Tung Chen

James Andrew Welker

Michael J Torla

Michael D Fitzsimmons

Mingle Sun

Darrell L Carder

Charles E Cannon

Amir K Daneshbeh

Geoffrey Paul Waters

Mohit Mongia

Srdjan Coric

John E Spittal, Jr

Jonathan Lutz

Gregory Schmidt

William C Moyer

Alexander Hoefler

John J Vaglica

Sandeep Jain

Nikila Krishnamoorthy

Joel Feldman

Steven E Cornelius

Evgeni Margolis

Erik D Swanson

Steven Tugeberg

Ruchir Chhabra

Wilhelmus J Philipsen

Troy E Mackie

Jie Gong

Alistair N Muir

Rodney D Ziolowski

Ronald B Harvey

Frank James

Various embodiments relate to an inline encryption engine in a memory controller configured to process data read from a memory, including: a first data pipeline configured to receive data that is plaintext data and a first validity flag; a second data pipeline having the same length as the first data pipeline configured to: receive data that is encrypted data and a second validity flag; decrypt the encrypted data from the memory and output decrypted plaintext data; an output multiplexer configured to select and output data from either the first pipeline or the second pipeline; and control logic configured to control the output multiplexer, wherein the control logic is configured to output valid data from the first pipeline when the second pipeline does not have valid output decrypted plaintext data available.

Processing pipeline where fast data passes slow data

Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and command logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a memory scrubber configured to cycle through memory locations and to read data from those locations; a region selector configured to determine when a memory location read by the memory scrubber is within an integrity checked memory region; a runtime integrity check (RTIC) engine connected to a read data path of the memory interface, wherein the RTIC engine is configured to calculate an integrity check value for the RTIC region using data read from the checked memory region by the memory scrubber; and a RTIC controller configured to compare the calculated integrity check value for the checked memory region to a reference integrity check value for the checked memory region.

Runtime integrity checking for a memory system

Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and control logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a read inline encryption engine (IEE) connected to the memory interface, wherein the read IEE is configured to decrypt encrypted data read from the memory; a key selector configured to determine a read memory region associated with the memory read request based upon a read address where the data to be read is stored, wherein the read address is received from the address and control logic; and a key logic configured to select a first key associated with the determined read memory region and provide the selected key to the read IEE.

Inline encryption/decryption for a memory controller

A semiconductor device including scan configuration circuitry that reconfigures latches of the device into a scan chain in response to assertion of a scan enable control signal, and scan control circuitry including delay circuitry, scan enable circuitry, evaluation circuitry, and scan reset circuitry. The scan reset circuitry keeps each of the secure latches in a predetermined reset state until assertion of both an evaluation signal and a scan mode signal. The delay circuitry includes N series-coupled flip-flops selected from different cell libraries detecting assertion of the scan mode signal and asserting a delay output signal only after N transitions of a test clock. The scan enable circuitry asserts the scan enable control signal when a scan enable command signal and the delay output signal are both asserted. The evaluation circuitry asserts the evaluation signal only when a collective state of the delay circuitry has achieved a predetermined state.

System and method of scan reset upon entering scan mode

A method of programming a memory includes selecting a logic state for programming a first bitcell of the memory. A first one-time-programmable (OTP) element of the first bitcell is programmed using a first set of conditions intended to achieve a first target resistance in accordance with the selected logic state which results in a first degree of programming of the first OTP element. A second OTP element of the first bitcell is programmed using a second set of conditions different from the first set of conditions intended to achieve a second target resistance in accordance with the selected logic state which results in a second degree of programming of the second OTP element, wherein the first and second degrees of programming are visually indistinguishable.

Memory having one time programmable (OTP) elements and a method of programming the memory

A method of encrypting data on a memory device includes receiving a memory transaction request at an inline encryption engine coupled between a processing core and switch fabric in a system on a chip (SOC). The memory transaction request includes a context component and a data component. The context component is analyzed to determine whether the data component will be stored in an encrypted memory region. If the data component will be stored in an encrypted memory region, the data component is encrypted and communicated to a location in the encrypted memory region. The location is based at least on the context component.

Systems and methods for data encryption

A semiconductor device includes a processing system including a section of power domain circuitry and a section of coin cell power domain circuitry. The coin cell power domain circuitry is configured to, when power is initially provided to the coin cell power domain circuitry, using power provided by a power management circuit as feedback to determine that the power management circuit provides the power in response to a power request signal being a toggle signal, and determine that the power management circuit provides the power in response to the power request signal being a pulse signal.

Data processing system with protocol determination circuitry

To securely configure an electronic circuit and provision a product that includes the electronic circuit, a first entity (e.g., a chip manufacturer) embeds one or more secret values into copies of the circuit. A second entity (e.g., an OEM): 1) derives a trust anchor from a code signing public key; 2) embeds the trust anchor in a first circuit copy; 3) causes the first circuit copy to generate a secret key derived from the trust anchor and the embedded secret value(s); 4) signs provisioning code using a code signing private key; and 5) sends the code signing public key, the trust anchor, and the signed provisioning code to a third entity (e.g., a product manufacturer). The third entity embeds the trust anchor in a second circuit copy and causes it to: 1) generate the secret key; 2) verify the signature of the signed provisioning code using the code signing public key; and 3) launch the provisioning code. The OEM can authenticate the second circuit copy using the first circuit copy and a challenge/response protocol.

Systems and methods for secure provisioning of production electronic circuits

A run-time integrity checking (RTIC) method compatible with memory having at least portions that store data that is changed over time or at least portions configured as virtual memory is provided. For example, the method may comprise storing a table of page entries and accessing the table of page entries by, as an example, an operating system or, as another example, a hypervisor to perform RTIC on memory in which, as an example, an operating system, as another example, a hypervisor, or, as yet another example, application software is stored. The table may, for example, be stored in secure memory or in external memory. The page entry comprises a hash value for the page and a hash valid indicator indicating the validity status of the hash value. The page entry may further comprise a residency indicator indicating a residency status of the memory page.

Continuous run-time integrity checking for virtual memory

Embodiments of electronic circuits, computer systems, and associated methods include a module that accesses memory using virtual addressing, the memory including local memory that is local to the module and nonlocal memory that is accessible via a system bus coupled to the module, the module including logic coupled to the local memory via a local bus. The logic is configured to receive a memory access specified to a virtual address, determine whether the virtual address is within the local memory, and direct the memory access either to the local memory via the local bus or to the nonlocal memory via the system bus based on the determination.

Virtualized local storage

Embodiments of an electronic circuit comprise a module, such as a security module, configured to perform cryptographic processing for a predetermined security protocol that includes random number checking. The security module is controlled by a descriptor that includes instructions that cause the security module to access a generated random number, compare the generated random number to a random number stored during a previous execution of the descriptor, and generate an error signal when the generated random number and the previous execution random number are equal.

Cryptographic processing with random number generator checking

A method and apparatus for testing operation of a random number generator (RNG) testing circuit are provided. In accordance with at least one embodiment, a first RNG output value obtained from a RNG is stored in a first register. In response to activation of a test mode to simulate a faulty RNG, the first RNG output value is stored in a second register. The first RNG output value in the first register is compared to the first RNG output value in the second register. In response to the comparing, a RNG failure signal is provided at a RNG testing circuit output of the RNG testing circuit. In accordance with at least one embodiment, sequential and combinational logic can simulate a faulty RNG. Accordingly, simulation of a faulty RNG may be performed to test a RNG testing circuit even when the RNG is not faulty.

Method and apparatus for testing a random number generator tester

Embodiments of electronic circuits enable security of sensitive data in a design and manufacturing process that includes multiple parties. An embodiment of an electronic circuit can include a private key embedded within the electronic circuit that is derived from a plurality of components including at least one component known only to the electronic circuit and at least one immutable value cryptographically bound into messages and residing on the electronic circuit, public key generation logic that generates a public key to match the private key, and message signing logic that signs messages with the private key.

Circuit for secure provisioning in an untrusted environment

An asymmetric cryptographic integrated circuitand a data processing devicein which the integrated circuitis used are disclosed. A security boundaryis confined to the interior of integrated circuit. A random number generatorwith a hardware entropy sourceand an arithmetic unitprogrammed through microcodeto perform a variety of cryptographically useful functions are included within security boundary. One of these functions is a primality tester. A controllerfor integrated circuitmay cause cryptographically sensitive data, such as large random prime numbers and a clear private key to be generated within the confines of security boundary. A symmetric key encryption engineis included within security boundaryand used to encrypt the clear private key so that a resulting encrypted private key may be stored outside security boundaryin a non-volatile memory

Asymmetric cryptographic device with local private key generation and method therefor

Embodiments include methods for securely provisioning copies of an electronic circuit. A first entity (e.g., a chip manufacturer) embeds one or more secret values into copies of the electronic circuit. A second entity (e.g., an OEM): 1) embeds a trust anchor in a first copy of the electronic circuit; 2) causes the electronic circuit to generate a message signing key pair using the trust anchor and the embedded secret value(s); 3) signs provisioning code using a code signing private key; and 4) sends a corresponding code signing public key, the trust anchor, and the signed provisioning code to a third entity (e.g., a product manufacturer). The third entity embeds the trust anchor in a second copy of the electronic circuit and causes the electronic circuit to: 1) generate the message signing private key; 2) verify the signature of the signed provisioning code using the code signing public key; and 3) launch the provisioning code on the electronic circuit. The electronic circuit can authenticate itself to the OEM using the message signing key pair.

Secure provisioning in an untrusted environment

Growing community of inventors

Phoenix, AZ, United States of America

Thomas E Tkacik