Texas Instruments Corporation

Thomas E Tang

Che-Chia Wei

Roger A Haken

Thomas C Holloway

David A Bell

Richard A Chapman

Clarence W Teng

Robert H Havemann

Monte A Douglas

Lee M Loewenstein

Ming J Hwang

Steve S Huang

Larry R Hite

Cheng-Eng D Chen

James G Bohlman

Rachelle J Bienstock

Dane E Bailey

A method and apparatus for deposition of an in-situ doped silicon film are disclosed. The deposition may be carried out in an LPCVD reactor, with the temperature of the chamber during deposition preferably closely above the decomposition temperature of silane gas. The preferred dopant source is tertiary butyl phosphine, since the deposition rate of in-situ doped silicon using this source is much greater than that using phosphine as the source, which allows low temperature deposition at reasonable rates. At a temperature of about 560.degree. Celsius, the phosphorous is better incorporated into the deposited film than in films deposited at higher temperatures, which allows the ratio of dopant gas to silane in the chamber to be lower; a low dopant ratio allows improved deposition thickness uniformity. The LPCVD reactor preferably has an injector tube therein which travels a distance within the reactor before its opening, through which the tertiary butyl phosphine passes. This allows the tertiary butyl phosphine to be fully heated, and therefore fully decomposed, prior to its introduction into the chamber. Such full decomposition of the dopant source gas further improves the uniformity of the thickness of the deposited film.

Method and apparatus for in-situ doping of deposited silicon

Preferred embodiments include silicon complementary MOSFETs with titanium silicided junctions (38, 58) and direct contacts of aluminum metallization (61, 62) to the p junctions (58) which avoids the high contact resistance of the silicide (60) to p silicon (58). Preferred embodiments also include silicided polysilicon lines without corresponding silicided MOSFET junctions.

Silicided structures having openings therein

A method and apparatus for sensing radiation 26 indicative of at least one process variable in a semiconductor process chamber 10 in which a reactant gas reacts to effect changes in a silicon wafer 12. The method comprises positioning a substantially transparent window 22 in a conduit 14 leading to the wafer 12 and then flowing the reactant gas in the conduit 14 past the window 22 and toward the wafer 12. The radiation 26 is then sensed through the window 22. In the preferred embodiment the window 22 is positioned with an optical path along the center axis of the conduit 14. Other systems and methods are also disclosed.

Method and apparatus for integrating optical sensor into processor

A vertical low pressure chemical vapor deposition, LPCVD, reactor that may be used to form deposition films on semiconductor wafers is disclosed. The vertical LPCVD reactor has a reaction chamber with a top portion and a bottom portion. A furnace heats the reaction chamber. Deposition gases are introduced into the bottom portion of the reaction chamber by a gas tube having a substantial portion heated by the furnace. Deposition gases are introduced into the top portion of the reaction chamber by a gas tube that is shaped so that a substantial portion of it overlies the top portion of the reaction chamber and is heated by the furnace. By heating the substantial portion of the gas tube overlying the top portion of the reaction chamber, the deposition gases passing through this tube are heated before they enter the top portion of the reaction chamber. This improves the uniformity of deposited films on semiconductor wafers residing in the top portion of the reaction chamber.

Vertical LPCVD reactor

A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These 'source/drain' regions 36 formed by using a silicon etch to form a recess, limiting the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusioins 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

Oxide-isolated source/drain transistor

A process for making CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat. A titanium nitride layer may be formed by depositing titanium metal everywhere, and then heating the integrated circuit structure in a nitrogen atmosphere. This process may also be used with other refractory metal nitride interconnect layers. In addition to titanium based thin film compositions, other metals can be substituted and used for direct-react silicidation and simultaneous formation of a conductive nitride to form local interconnects, including molybdenum, tungsten, vanadium, cobalt, and others.

Process for making CMOS device with both P+ and N+ gates including

An SRAM using TiN local interconnects. This permits the moat parasitic capacitance to be reduced, and also avoids use of metal jumpers, resulting in increased density.

SRAM with local interconnect

A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These 'source/drain' regions 36 are formed by using a silicon etch to form a recess, lining the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusions 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

Method of making oxide-isolated source/drain transistor

The present invention provides a method for inhibiting the oxidation of a titanium layer during the direct reaction of the titanium with exposed silicon areas of an integrated circuit. In one embodiment of the present invention, a titanium nitride layer is formed on the surface of the titanium layer in the reactor where the titanium layer is deposited. The titanium nitride layer provides an effective barrier against oxidation. Thus, the formation of titanium dioxide is inhibited. In addition, in those areas where titanium nitride local interconnect is to be formed between diffused areas, the extra thickness provided by the top titanium nitride layer adds in the integrity of the conductive layers. By conducting the silicidation in a nitride atmosphere, diffusion of the nitride from the titanium nitride layer into the titanium layer and substitution of those lost nitrogen atoms by the atmosphere occurs thus providing a blocking layer for the formation of titanium silicide shorts.

Selective silicidation process using a titanium nitride protective layer

A CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat.

CMOS device with both p+ and n+ gates

A process for forming shallow silicided junctions includes the step of sputtering a layer of titanium (28) over a moat region to cover a gate electrode (18) and a sidewall oxide (22) formed on the sidewalls of the gate electrode (18). The titanium is reacted with exposed silicon regions (24) and (26) to form silicide layers (30) and (32) and then dopant impurities are implanted into the substrate (10) prior to stripping the unreacted titanium. The unreacted titanium (36), (38), or (40) functions as a mask to both offset the implanted regions from the channel region (20) under the gate electrode (18) and also to prevent impurities from entering the substrate at regions outside the defined moat region.

Process for formation of shallow silicided junctions

A local interconnect system for VLSI integrated circuits. After titanium is deposited for self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a hardmask is deposited and patterned over the titanium. When a conductive titanium nitride layer is formed overall, it will already be patterned according to this hardmask.

Local interconnect

A cap oxide (or oxide/nitride) prevents silicon outdiffusion during the reaction step which forms direct-react titanium silicide.

Oxide-capped titanium silicide formation

A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. A second titanium layer is then deposited overall and again reacted, to thicken the nitride layer without increasing the thickness of the silicide layers. This conductive layer is patterned and etched to provide local interconnects with a sheet resistance of the order to ten ohms per square, and also etch stops. Moreover, this local interconnect level permits contacts to be misaligned with the moat boundary, since the titanium nitride local interconnect layer can be overlapped from the moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide. This local interconnect capability fulfills all of the functions which a buried contact capability fulfill, and fulfills other functions as well.

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Dallas, TX, United States of America

Thomas E Tang