International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Thomas E Stanley

Bernd Lamberts

Martin Aureliano Hassner

Daniel Jonathan Auerbach

Karl Gong

Joseph Silva

Yue Ming Tang

Hin-Ching Hubert Chan

A method for determining a write inhibit threshold value for at least one head of a file during the file manufacturing process is disclosed. The method includes qualifying a test track for use in the determining of the write inhibit threshold value. The method further includes performing a write inhibit threshold determination process to obtain the write inhibit threshold value and then storing the write inhibit threshold value for use with the at least one head of the file.

Method for determining unique write inhibit thresholds for individual heads for maximizing file servo performance

A generic manufacturer-independent method to produce a metric of hard disk drive performance includes executing accesses from a reference sector on disk to several equidistantally-spaced target sectors, and recording the times of the accesses. These times are then ordered and used to generate shortest access times along with probabilities of achieving those access times, losing a disk revolution while accessing the target sector, and losing a disk revolution while executing a read/write operation.

System and method for determining hard disk drive performance

A method for adaptively controlling the error correction redundancy is presented. The method utilizes test information collected at the file characterization test to adaptively determine the quantity of error correction code bytes needed at a multitude of levels of the error correction scheme. The error correction needed at the sub-block level is determined from a measurement of the back ground noise floor. At the block level the file characterization is specific to zones identified by head, disk, sector and cylinder. The formatting efficiency of the drive is increased by adaptively linking the length of the error correction code to the location of the zone. By measuring the error rate (E/R) on a per zone basis and comparing this rate to the disk level E/R the ECC can be optimized on a per-zone basis. The method is implemented by modeling a probability distribution as a first polynomial having a basis, converting the first polynomial to a second polynomial having a different basis, and by defining a Hamming distance distribution from the second polynomial. In a preferred embodiment, modeling the probability distribution includes modeling as a Charlier polynomial, and converting to the second polynomial includes converting to a Krawtchouck polynomial, and using connection coefficients that are calculated recursively.

Programmable multi-level track layout method and system for optimizing ECC redundancy in data storage devices

A method and apparatus for monitoring track misregistration that is quicker and that is not limited to worst case assumptions. The present invention includes a first memory for accumulating position error signals for a head to produce an accumulated value, a processor for normalizing the accumulated value to produce a normalized result at a predetermined trigger event and a second memory for adding the normalized result therein to produce a running sum; wherein the head is positioned using the running sum. The processor resets the first memory when the normalized result is produced. A counter is provided for incrementing a count value after each position error signal is added to the first memory. The processor normalizes the accumulated value according to the count value of the counter, and the processor resets the counter as a result. In addition, the processor may normalize the accumulated value according to a population mean and a variance associated with the data storage system. The trigger event may include the accumulated error value reaching a predetermined threshold or a servo seek to the next track. The process may be initiated using a self-test command.

Method and apparatus for monitoring track misregistration

A method and apparatus for addressing a plurality of AT Attachment, Integrated Drive Electronics (ATA/IDE) disk drive assemblies from a single PC/AT thereby allowing the performance of manufacturing tests on multiple IDE drives using the ISA bus. Other drive assemblies are address during the substantial PC/AT CPU and I/O idle time available during the testing of a selected drive assembly. The system includes a PC/AT computer having an ISA bus, a plurality of ATA/IDE disk drives, and a multi-master card disposed between the PC/AT and the plurality of disk drives. The multi-master card includes an IDE controller card with a parallel port. Signals are generated to select one of the plurality of disk drives and ISA bus signals are routed to the selected disk drives. All the disk drives are disabled but the selected disk drive and a three bit signal line is used to select the disk drive for testing. Test capabilities are provided for in a standard, local, and remote mode of operation. The addressing scheme allows all drives to be addressed as master drives and each master on the bus can have a slave attached.

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Gilroy, CA, United States of America

Thomas E Stanley