At&t Bell Laboratories

Thomas E Seidel

William T Lynch

Joseph Lebowitz

It is known to utilize dielectric-filled trenches in a CMOS integrated-circuit device to achieve electrical isolation between adjacent n-channel and p-channel regions. In that way, latchup-free operation of the device is ensured. But inversion effects along the walls of the trenches can cause high leakage currents, undesirably high parasitic capacitances and even shorting together of source/drain regions. In accordance with the invention, a nonlithographic technique including selective anodic oxidation is employed to selectively mask the sidewalls of the trenches. Each sidewall can then be independently doped thereby effectively eliminating the possibility of inversion occurring therealong.

Method of making and selectively doping isolation trenches utilized in

Selective wet or plasma anodization is utilized for forming a relatively thick dielectric layer only at the bottoms of trenches included in DRAM and/or CMOS devices. In that way, the electrical characteristics of trenches that include bottoms having surface roughness and/or sharp or irregular corners are significantly improved. Additionally, electrically isolated capacitor structures in elongated trenches formed in DRAM devices are thereby made feasible.

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Carlsbad, CA, United States of America

Thomas E Seidel