Tellabs Operations, Inc.

Advanced Micro Devices Corporation

Ati Technologies Ulc

Thomas E Ryan

Terrence J Tanis

Greg Sadowski

Mark E Boduch

John Belden Kenney

Daniel J Marchok

Spencer Montgomery Gold

Haibo Liu

Paul Chow

Daniel Wong

Wai Ki Lo

Arun B Hegde

Stephen Edward Smith

Charles H Daugherty

Gary L Davis

Robert C Klein

Steven Metzler

Data stored in SRAM cells are periodically flipped e.g., before long idle periods. Operating the memories in both a 'flipped' mode and a 'non-flipped' mode helps cause the Bias Temperature Instability (BTI) degradation to be symmetric, thereby not degrading the Static Noise Margin (SNM) degradation of the cells. The data stored in memory locations is flipped by reading out the data, inverting the read out data, and writing the inverted read out data into the memory locations until the memory locations of the SRAM have been read out and written. When the memory operates in flipped mode, data read from and written into the memory is inverted to maintain transparency to the memory user. After operating the data in flipped mode for a period of time, the flipped data stored in the memory is reflipped to operate in the non-flipped mode.

Bit-flipping in memories

The subject matter disclosed herein provides methods and apparatus, including computer program products, for providing intermediate compression or decompression for use with a video decoder and a memory. In one aspect, there is provided a method including receiving information to enable compression of a macroblock. At an intermediate section coupled to a video decoder and a memory, a macroblock may be compressed. The compression of the macroblock may be based on the received information. The compressed macroblock may be provided to memory. Related apparatus, systems, methods, and articles are also described.

Adaptive compression of video reference frames

In one aspect, there is provided a video decoder including a first write port to write uncompressed video data to a first buffer in a first format adapted based on an input required by the video decoder and to suppress writing to the first buffer. The video decoder also includes a second write port to write uncompressed video data to a second buffer in a second format adapted to provide the uncompressed video data for subsequent processing external to the video decoder.

Video decoder with adaptive outputs

A method and apparatus are provided for horizontally slicing a multi-stage switching fabric having transmission inputs and transmission outputs to and from the switch fabric. The switching fabric includes switch elements arranged in at least first and second stages, each switch element having element inputs and outputs with each switch element being configured to join one of the element inputs with an associated one of the element outputs. The switch fabric includes a first logic device that contains a stage-1 subset of the switch elements that is arranged within, and configured to operate as part of, the first stage. The first logic device also contains a stage-2 subset of the switch elements arranged within, and configured to operate as part of, the second stage. The switch fabric includes a second logic device that contains a stage-1 subset of the switch elements that is arranged within, and configured to operate as part of, the first stage. The second logic device also contains a stage-2 subset of the switch elements that is arranged within, and configured to operate as part of, the second stage. The first and second logic devices are physically discrete from one another.

Method and apparatus for horizontally slicing a multi-stage switch fabric

Multistage switching for mixed SONET VT traffic, such as VT1.5s and VT2s, is accomplished by employing an input time switch, a space switch and an output time switch. The input time switch and output time switch include VT1.5 time switches arranged to alter the time order of the input VT1.5s and VT2 time switches arranged to alter the time order to the input VT2s. The space switch includes a VT1.5 space switch arranged to order the input VT1.5s with respect to output channels in an output channel order different from the input channel order of the VT1.5s. The space switch also includes a VT2 space switch arranged to order the input VT2s with respect to output channels in an output channel order different from the input channel order of the VT2s.

Communication multistage switching techniques

A method and apparatus are provided for horizontally slicing a multi-stage switching fabric having transmission inputs and transmission outputs to and from the switch fabric. The switching fabric includes switch elements arranged in at least first and second stages, each switch element having element inputs and outputs with each switch element being configured to join one of the element inputs with an associated one of the element outputs. The switch fabric includes a first logic device that contains a stage-subset of the switch elements that is arranged within, and configured to operate as part of, the first stage. The first logic device also contains a stage-subset of the switch elements arranged within, and configured to operate as part of, the second stage. The switch fabric includes a second logic device that contains a stage-subset of the switch elements that is arranged within, and configured to operate as part of, the first stage. The second logic device also contains a stage-subset of the switch elements that is arranged within, and configured to operate as part of, the second stage. The first and second logic devices are physically discrete from one another.

A static storage element distorts metastable feedback signals in an unbalanced feedback loop with the resulting metastable signals eroding and being suppressed as they circulate in the loop. The element exhibits a predetermined output state subsequent to suppression of the eroded signals.

Fast ring-out digital storage circuit

An improved phase-lock loop circuit comprising a phase detector, a loop filter, and a voltage controlled oscillator. The phase detector samples the phase-lock loop input signal at various points in a cycle of the phase-lock loop output signal and outputs a signal representative of the point of the phase-lock loop output cycle at which a logic state transition of the input signal is detected. In addition, a self-sweeping autolock circuit interacts with the loop filter in such a manner that the self-sweeping autolock circuit commands the loop filter to sweep its output signal when phase-lock is absent and the loop filter halts the sweep of its output signal when phase-lock is acquired.

Self-sweeping autolock PLL

Input interfaces convert a predetermined data frame structure, such as a Sonet STS-1, into an internal format comprising a predetermined number of rows and columns, the rows being a multiple of a number evenly divisible into the bytes contained in the internal frame format. A time-space switch switches the frame format while storing a row of bytes in a data memory. Output interfaces convert the switched data to the same type of data frame format received at the input.

Growing community of inventors

Boylston, MA, United States of America

Thomas E Ryan