Synopsys, Inc.

Citrix Systems, Inc.

Thomas E Roth

David J Giramma

Oliver W Kozber

Josh Thomas Gray

Michael G Robinson

David K Johnson

Described embodiments provide systems and methods for cross protocol association using internet addresses for metadata association. An association between IPv4 addresses and IPv6 addresses can determined and used to bridge metadata from collection context in a first protocol into usage for a second protocol. A server can monitor a plurality of handshake exchanges to generate the association between IPv4 addresses and IPv6 addresses for a device or group of devices. The handshake exchange can include an IPv4 address, an IPv6 address, or both an IPv4 address and an IPv6 address for a respective device. The handshake exchanges can include a unique identifier corresponding to the respective device. The server can use the association to generate a mapping linking a range of IPv4 addresses to a range of IPv6 addresses corresponding to the same device. The mapping can be used to associate metadata to devices within the same ranges.

Cross protocol association for internet addresses for metadata association systems and methods

Described is a circuit modifier, network, and method for use with an event-driven digital logic simulator for enforcing consistent evaluation of input pin changes at state elements. The invention automatically interposes a fictitious 0-delay defer agent or processor, at the input pin to state elements such as D Flip-Flops. The interposition of the defer agent is handled by the simulator as follows. Defer agents schedule events related to input state changes on a special time or task queue which is not processed until after all other events have been executed for the current time, including any extra iterations caused by 0-delay scheduling activity. Defer agents or processors are placed in a simulation network just prior to one or more of the input pins of state elements, the effect of which is to delay events that normally would propagate to the input pin of a state element until all other normal simulation events are processed. Once the normal simulation events have been executed, the defer events are executed which permits the inputs of the state elements to change after other simulation events have been executed, thereby ensuring consistent evaluation of pin changes at state elements.

Digital simulator circuit modifier, network, and method

Described is an invention that provides an efficient selection of timing statements for a logic cell in response to cell pin activity when such cell is implemented as one or more instances of simulator primitives. It does so by defining a first storage structure coupled with a logic processor coupled, in turn to a second storage structure. First storage structure defines plural bitfield arrays corresponding with a cell pin and a possible logic level or state, each bitfield array having an entry for an old or a former state of the pin, a next or new state of that pin and a stable state of that pin and each bitfield array defining an index to one or more memory-based look-up tables defining the number of a timing and/or constraint parameter for the given pin of the logic cell. Such timing parameters describe a delay between two pins of the cell, while such constraint parameters describe timing constraints for the logic cell such as setup times, hold times and minimum pulse width times. In accordance with a preferred embodiment of the invention, a set of rules is enforced by the logic processor during a digital logic simulation run to ensure that appropriate timing and constraint for the logic cell is maintained. Zero-delay timing is used across a collection of instances within a logic cell, thereby to ensure that all timing and constraint analysis is performed at cell boundaries. Timing is evaluated after all simulation activity for a given time frame has ceased, and such is done preferably by scheduling scrubber events that are executed as tasks on a defer queue that is processed at the end of the digital logic simulation activity.

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Portland, OR, United States of America

Thomas E Roth