International Business Machines Corporation

Globalfoundries Inc.

Semiconductor Components Industries, LLC

Thomas E Morf

Marcel A Kossel

Danny Elad

Jonas R Weiss

Peter Mueller

Dan Corcos

Martin L Schmatz

Pier Andrea Francese

Lukas Kull

Matthias Fertig

Thomas Pflueger

Nikolaj Moll

Noam Kaminski

Mridula Prathapan

Ofer Markish

Bernhard Klein

Bruno Michel

Mircea R Gusat

Michel Despont

Abdullah Serdar Yonar

Maria Soimu

Hayden C Cranford, Jr

Bernd W Gotsmann

Thomas Helmut Toifl

Daniel Michael Kuchta

Christian I Menolfi

Evgeny Shumaker

Cezar Bogdan Zota

Alessandro Cevrero

Ilter Özkaya

Marc Seifried

Roi Carmon

Matthias Braendli

Silvan Wehrli

Heike E Riel

David Goren

Mehmet Soyuer

Benny Sheinman

Tobias Lamprecht

Jakob Vovnoboy

Israel Berger

Karl-Heinz Brenner

Bogdan Cezar Zota

Matthias Mergenthaler

Eunjung Cha

Nkolaj Moll

Martin Kreissig

Maximilian Auer

Christian Menofli

Sebastien Ragot

Provided is a low noise amplifier circuit for a quantum computer. The low noise amplifier circuit comprises a plurality of input stages, a shared output stage, and a voltage controller. Each input stage is coupled to one or more qubits. The shared output stage is coupled to the plurality of input stages. The voltage controller is coupled to the plurality of input stages and the shared output stage. The voltage controller is configured to selectively activate an input stage of the plurality of input stages in order to read a qubit coupled to the input stage.

Parallelized low noise amplifiers for a quantum computer

A superconductor transistor structure includes a source electrode and a drain electrode on a same plane as the source electrode. There is a channel region on top of the source and drain electrodes and configured to carry a current. A gate structure comprising a metallic material is on top of the channel region. The source and drain are located on a side that is opposite to that of the gate structure, with respect to the channel region.

High electron mobility transistor with source and drain electrodes below the channel

The invention is notably directed to a voltage-to-time converter comprising a first interleaving stage configured to perform a sampling of an input voltage, thereby generating a first set of sampled voltage signals. The first interleaving stage is further configured to perform a first voltage-to-time conversion in an interleaved manner, thereby generating a first set of time-interleaved signals in the time domain. A second interleaving stage is configured to perform a time-to-voltage conversion of the first set of time-interleaved signals, thereby generating a second set of sampled voltage signals. The second interleaving stage is further configured perform a second voltage-to-time conversion in an interleaved manner, thereby generating a second set of time-interleaved signals in the time domain. The invention further concerns a related design structure and a related method.

Time domain interleaving

A computer-implemented method of reducing an impact of stray magnetic fields on components of a quantum computing chip is disclosed. The computer implemented method includes applying a first current signal to a first component of a quantum computing chip, whereby the first component generates a stray magnetic field impacting an operation of a second component of the quantum computing chip. The computer implemented method further includes applying a compensation current signal to a shielding circuit of the quantum computing chip, the compensation current signal generated according to a predetermined function of the first signal, to magnetically shield the second component from the stray magnetic field generated by the first component.

Semi-active magnetic shielding for qubit unit components of quantum computing apparatuses

A hierarchical time step generator circuit is configured to be used for a time-based analog-to-digital converter. The hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal. The time-based analog-to-digital converter is configured to be controlled to digitize the input signal by the multiphase clock signals. The hierarchical time step generator includes a first level time step generator configured to generate the a set of first level multiphase signals in response to receiving the reference clock signal a phase interpolator circuit configured as second level to generate second level clock signals between each of the first level clock signals and a third level configured to generate the third set of multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of the second level clock signals.

Sampling circuit with a hierarchical time step generator

The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.

Control unit for qubits

Disclosed herein is an analog-to-digital converter circuit configured for digitizing an analog input signal. The analog-to-digital converter comprises an analog input configured for receiving the analog input signal. The analog-to-digital converter circuit further comprises at least one sub-ADC connected to the analog input signal, wherein the at least one sub-ADC is configured to output at least one encoded output vector in response to receiving the analog input signal. The analog-to-digital converter circuit further comprises a lookup circuit comprising a nested lookup table. The lookup circuit is configured to select an output value from the nested lookup table using the at least one encoded output vector, wherein the lookup circuit is configured to provide the output value as the digitization of the analog input signal.

Analog-to-digital converter circuit with a nested look up table

An electrostatic discharge (ESD) protection circuit is configured to protect a target circuit that operates in a cryogenic temperature is provided. The ESD protection circuit connects a terminal of the target circuit and a ground potential with no connection to a bias potential. When the ESD protection circuit receives a voltage potential at the terminal of the target circuit, the ESD protection circuit (i) disallows electrical current to flow through from the received voltage potential when the device is at a cryogenic temperature and (ii) allows electrical current to flow through from the received voltage potential when the device is at a room temperature.

Semiconductor quantum device ESD protection

An electrostatic protection device for protecting an input port of an electronic circuit. The electrostatic protection device includes a first stacked coil, a second stacked coil, and an input terminal, wherein the second stacked coil is inductively coupled to the first stacked coil. The first stacked coil comprises a first coil input connected to the input terminal, and a first coil output port connected to a lower frequency ESD protection circuit, and wherein the lower frequency ESD protection circuit comprises a lower frequency output. The second stacked coil comprises an output port connected to a higher frequency ESD protection circuit, and wherein the higher frequency ESD protection circuit comprises a higher frequency output.

Electrostatic protection device

Systems and methods directed to a quantum processing apparatus are provided. The apparatus comprises M solid-state qubits, where M&#x3e;1, and control electronics, which are connected to the solid-state qubits. The control electronics comprise one or more qubit readout circuits, where each of the qubit readout circuits is connected to at least one of the solid-state qubits and comprises a downsampling analog-to-digital converter (hereafter DSADC). Each DSADC is configured to downsample analog signals obtained from the at least one of the solid-state qubits. Such a DSADC operates in the nNyquist zone of the spectrum of the analog signals obtained, so as to down-convert such analog signals from the nNyquist zone to the mNyquist zone of the spectrum, where n&#x3e;m&#x2265;1, prior to sampling the analog signals to convert them into digital signals, in operation. One or more embodiments of the invention are further directed to a related method of operating such a quantum processing apparatus.

Quantum processing apparatus with downsampling analog-to-digital converter

An electrostatic protection device for protecting an input port of an electronic circuit. The electrostatic protection device includes a first stacked coil, a second stacked coil, and an input terminal, wherein the second stacked coil is inductively coupled to the first stacked coil. The first stacked coil comprises a first coil input connected to the input terminal, a first coil output port connected to a lower frequency ESD protection circuit, and a first coil termination port connected to a termination load, and wherein the lower frequency ESD protection circuit comprises a lower frequency output. The second stacked coil comprises an output port connected to a higher frequency ESD protection circuit, and wherein the higher frequency ESD protection circuit comprises a higher frequency output. The electrostatic protection device comprises a summation circuit configured for outputting a summation of the higher frequency output and the lower frequency output.

A quantum processing system may include one or more superconducting qubits and a qubit controller for controlling the one or more qubits. The qubit controller includes a radio frequency generation unit comprising electronic components, which are altogether configured to generate modulated RF signals. The controller also includes a phase locked loop unit maintaining a reference clock for two or more of the components of the RF generation unit, and a timing controller including an absolute timing register, the latter accessed by the reference clock, in operation. The qubit controller comprises a sequencer coupled to the timing controller to synchronize said two or more of said components by maintaining a coherent signal for said two or more of said components, the coherent signal phase matched to the one or more qubits, to drive and/or read out the one or more qubits via modulated signals generated by the synchronized components, in operation.

Quantum processing system including a modulated RF generator with synchronized components

A novel system that allows for 3D radar detection that simultaneously captures the lateral and depth features of a target is disclosed. This system uses only a single transceiver, a set of delay-lines, and a passive antenna array, all without requiring mechanical rotation. By using the delay lines, a set of beat frequencies corresponding to the target presence can be generated in continuous wave radar systems. Likewise, in pulsed radar systems, the delays also allow the system to determine the 3D aspects of the target(s). Compared to existing solutions, the invention, in embodiments, allows for the implementation of simple, reliable, and power efficient 3D radars.

High spatial resolution 3D radar based on a single sensor

A quantum computer hardware apparatus may include a first stage, which is connected to one or more signal generators, and a second stage adapted to be cooled down at a lower temperature than the first stage. Superconducting qubits are arranged in the second stage. The signal generators are configured, each, to generate radio frequency (RF) signals to drive the qubits, in operation. The apparatus may further include an intermediate stage between the first stage and the second stage, wherein the intermediate stage comprises one or more coolable filters, the latter configured for thermalizing RF signals from the signal generators. Related methods for thermalizing radio frequency signals in a quantum computer hardware apparatus are also disclosed.

Quantum computer hardware with reflectionless filters for thermalizing radio frequency signals

Aspects of the invention provide for an electrostatic protection device for protecting an input port of an electronic circuit. The electrostatic protection device includes a stacked coil assembly with four ports. The electrostatic protection device further includes a human body model ESD protection circuit, a charge device model ESD protection circuit, and an impedance matching circuit. The human body model ESD protection circuit, the charge device model ESD protection circuit, and the impedance matching circuit are connected to separate ports selected from the four ports.

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Einsiedein, Switzerland

Thomas E Morf