Ast Research, Inc.

Western Digital Technologies, Inc.

Vtech Industries, Inc.

Thomas E Ludwig

Thomas W Craft

Bradley T Herrin

John Edward Maroney

Edwin Dale Barnes

David N Still

A storage system including a first boot drive configured to store an operating system, one or more data drives configured to store user data, the one or more data drives distinct from the first boot drive, and a controller configured to detect when a second boot drive is added to the storage system, and automatically configure the first boot drive and the second boot drive in a redundant array of independent disks ('RAID') configuration when the controller detects that the second boot drive is added to the storage system.

Automatic raid mirroring when adding a second boot drive

The invention relates to an improved RAID initialization method. Prior to operational use, the device undergoes a forced rebuild that supplements the initialization process. Since the RAID device is in a pre-operational condition, the data does not have to be preserved. Thus, the forced rebuild can employ bulk read and write operations using large portions of data. The forced rebuild results in RAID protection data that can be produced more quickly and is more coherent than what is created by quick initialization. Accordingly, embodiments provide a device that is delivered in an initialized state that is safer and more stable for use by the user.

Fast initialization of storage device

A computer system includes a microprocessor that is electrically connected to a first synchronous bus operating in synchronism with a first clock signal at a first clock frequency. A second synchronous bus operates in synchronism with a second clock signal at a second clock frequency and provides electrical communication to a number of peripheral devices. An asynchronous bus provides data communication between the first and second synchronous bus using handshaking signals so that the first and second clock signals operate independently of each other. The operating frequency and other parameters of the microprocessor and the first synchronous bus can be changed without requiring any changes to the second synchronous bus so that the microprocessor and the first synchronous bus can take advantage of advances in technology while allowing the second synchronous bus and the associated peripheral devices to remain compatible with previous versions of the computer system.

Microcomputer architecture utilizing an asynchronous bus between

A high speed/low overhead bus arbitration apparatus for allocating system bus mastership in a system containing two processing devices. The apparatus includes control logic which controls the access of each of the processing devices to the system bus. The apparatus further includes a multiplexer for selecting the control information presented on the system bus based upon the state of the control logic. The apparatus finally includes a latch for alternatively passing through to and latching onto the system bus, based upon the state of the control logic, an address, which is driven by only one of the processing devices. The control logic transfers access to the system bus from the first processing device to second when the second requests access and the bus is not busy, preventing both processing devices from contending for the system bus by forcing the driving processor device to relinquish the address lines prior to completion of the current bus cycle. The control logic further transfers access to the system bus back to the first processing device when the first requests access and the bus is not busy.

High speed/low overhead bus arbitration apparatus and method for

An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.

Shared memory bus system for arbitrating access control among contending

A circuit for synchronizing an asynchronous input signal with an internal time base clock operates at a high frequency. The circuit includes an input flip-flop that receives the input signal and an output flip-flop that provides an output signal that is synchronized with the internal time base clock. The input flip-flop and the output flip-flop are interconnected via logic circuitry so that any instability on the output of the input flip-flop caused by failure of the input signal to satisfy the setup and hold conditions of the input flip-flop are isolated from the output of the output flip-flop. The output of the output flip-flop is a stable signal that is synchronized with the internal time base clock.

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Irvine, CA, United States of America

Thomas E Ludwig