Q-dot, Inc.

University of Michigan

Teqnovations, LLC

Other

Thomas E Linnenbrink

Stephen D Gaalema

Charles S Desilets

Marshall K Quick

Matthew N O'Donnell

Steven R Freeman

Marc A Morin

Mark Anthony Wadsworth

David W Gardner

David A Gradl

Brian P Higgins

Timothy G O'Shaughnessy

Lyle Whelchel

R Carver Anderson

Rebecca S Reed

Thomas K Bohley

Kerry D Rhea

Peter C Roberts

A transmission line is provided with a fixed physical length and a programmable electrical length for achieving a programmable time delay. The transmission line can include a dielectric and a biasing device disposed across the dielectric, and the biasing device can dynamically and continuously vary an absolute level of a bias voltage across the dielectric to vary a dielectric constant of the dielectric, which can vary a time delay of the transmission line. In some embodiments, the biasing device can modulate the bias voltage from a positive voltage to a negative voltage at a frequency and with waveform characteristics that prevent such modulation from interfering with a signal propagating through the dielectric, that prevent the bias voltage from unintentionally varying the time delay of the transmission line when the absolute level of the bias voltage is constant, and that prevents ion impurities within the dielectric from accumulating on bias electrodes.

Active, electronically scanned array antenna

An improved active, electronically scanned array antenna that employs programmable time delays in the transmission feed lines to form timed arrays is provided. A timed array can be implemented as a nested set of transmission lines, and the programmable time delay can be realized as or in each of the transmission lines such that each transmission line can have a fixed physical length and a programmable electrical length.

A method and apparatus are provided for reducing distortion in a dynamically delayed digital sample stream of an imaging system. The method includes the steps of delta-sigma modulating an input analog signal of the imaging system at a frequency above the Nyquist frequency of the input analog signal to generate a digital sample stream and changing a length of the sample stream to delay a portion of the sample stream while maintaining synchronism between a delta-sigma modulator and a demodulator of the system.

Beamformed ultrasonic imager with delta-sigma feedback control

An acoustic/video processing stack of a plurality of substantially identical acoustic/video processing stacks is provided for attachment to a processing stack backplane and which together generate a VGA signal for display of a three-dimensional acoustic image. The acoustic/video processing stack includes a two-dimensional array of transducer elements, a companion chip block coupled to and adapted to transceive acoustic signals under a time-division multiplexed format through the transducer elements and to provide a portion of the VGA signal together generated by the plurality of acoustic/video processing stacks and a backing block disposed between the two-dimensional array and companion chip block and adapted to acoustically isolate the two-dimensional transducer array from the companion chip block, said companion chip block and backing block being of a size and diameter substantially the same as the two-dimensional transducer array.

Acoustic lens-based swimmer's sonar

An apparatus and method of equalizing a first and second charge packet. The apparatus includes a charge splitter for splitting the first charge packet into a third charge packet on the first side of the charge splitter and a fourth charge packet on the second side of the charge splitter. The second charge component is split into a fifth charge component on the first side of the charge splitter and a sixth charge component on the second side of the charge splitter. The apparatus includes a charge combiner for adding the third and sixth charge packets and the fourth and fifth charge packets.

CCD charge splitter

An apparatus and method of equalizing a first and second charge packet. The apparatus includes a charge splitter for splitting the first charge packet into a third charge packet on the first side of the charge splitter and a fourth charge packet on the second side of the charge splitter. The second charge component is split into a fifth charge component on the first side of the charge splitter and a sixth charge component on the second side of the charge splitter. The apparatus includes a charge combinet for adding the third and sixth charge packets and the fourth and fifth charge packets.

An improved CCD imaging array is disclosed which is capable of operating at 10,000 frames-per-second. The imager consists of an array of 512.times.512 pixels having 16 serial output channels which provides a composite output data rate up to 250 Megasamples/second. The serial output registers are constructed from peristaltic CCDs, each having a GaAs FET output circuit bump-mounted to the silicon substrate. A four-layer pinned photodiode is utilized as the photodetector, and each photodiode has its own antiblooming drain. The antiblooming gates double as an optical shuttering device. Sample-and-hold output circuitry is also provided.

High-speed peristaltic CCD imager with GaAs fet output

The high speed data pathway system is used to convey data signals to integrated circuits connected to mother and daughter boards. The integrated circuits include a package and an integrated circuit chip carried by the package. An internal transmission line is carried by the package and coupled to the integrated circuit chip. The package includes both input and output connections for the internal transmission line. A high speed pathway is formed by serially connecting the internal transmission lines with external transmission lines to form a unified transmission medium. Advantageously, the internal transmission lines, external transmission lines and the connection between them have substantially corresponding characteristic impedances.

High-speed data supply pathway systems

A symmetric pipelined charge-mode analog to digital converter including a signal-reference CCD channel having a plurality of charge storage stages that are arranged in a serial configuration to carry the signal and reference charges, and a CCD digital channel. A set of two step comparators coupled to the signal-reference channel first senses and stores the signal charge and then senses and compares the reference charge to the signal charge. In the first stage, an initial reference charge is used, and in subsequent stages, an increment of one half the previous stage increment is added to the reference. In addition, at each stage, a charge increment equal to the previous reference increment is conditionally added to the signal charge and a corresponding bit in the digital channel is conditionally set responsive to the comparator. Thus, if the total signal charge is less than the total reference charge at a stage, the charge increment is added to the signal charge in the signal-reference channel, and a corresponding digital bit charge is zeroed in the digital channel. Conversely, if the total signal charge is larger than the told reference charge at a stage, the charge increment is not added to the signal charge and a corresponding digital bit charge is set to represent a one in the digital channel. One configuration provides a differential symmetric architecture wherein two signal-reference channels simultaneously feed a dual symmetric comparator providing enhanced symmetry thereby reducing threshold and offset sensitivity and susceptibility to environmental factors such as ionizing radiation.

Charge-mode analog to digital converter

A symmetric pipelined charge-mode analog to digital converter including a signal-reference CCD channel having a plurality of charge storage stages that are arranged in a serial configuration to carry the signal and reference charges, and a CCD digital channel. A set of two step comparators coupled to the signal-reference channel first senses and stores the signal charge and then senses and compares the reference charge to the signal charge. In the first stage, an initial reference charge is used, and in subsequeant stages, an increment of one half the previous stage increment is added to the reference. In addition, at each stage, a charge increment equal to the previous reference increment is conditionally added to the signal charge and a corresponding bit in the digital channel is conditionally set responsive to the comparator. Thus, if the total signal charge is less than the total reference charge at a stage, the charge increment is added to the signal charge in the signal-reference channel, and a corresponding digital bit charge is zeroed in the digital channel. Conversely, if the total signal charge is larger than the told reference charge at a stage, the charge increment is not added to the signal charge and a corresponding digital bit charge is set to represent a one in the digital channel. One configuration provides a differential symmetric architecture wherein two signal-reference channels simultaneously feed a dual symmetric comparator providing enhanced symmetry thereby reducing threshold and offset sensitivity and susceptibility to environmental factors such as ionizing radiation.

Growing community of inventors

Monument, CO, United States of America

Thomas E Linnenbrink