Diamond Multimedia Systems, Inc.

Thomas E Kilbourn

Sridhar Begur

Daniel B Gochnauer

Adrian Lewis

Donald J Spencer

James K Gifford

A data channel controller, coupleable to a base computer system including a base memory, for managing the transport of multiple data streams through a base system interface including a first buffer, a pool memory including a plurality of second buffers, and one or more peripheral devices each having a third buffer. An arbiter system is coupled to said pool memory for selectively enabling the transfer of data with respect to a predetermined first buffer in response to first and second request signals. The peripheral devices operate to transport data through their third buffers with respect to a peripheral interfaces characterized as each having a predetermined data transfer rate. The peripheral devices first request signals to the arbiter system under first predetermined conditions with respect to the presence of data in corresponding third buffers to obtain a transfer of data between corresponding second and third buffers. The base system interface provides the second request signal under second predetermined conditions with respect to the presence of data in the second buffers to obtain corresponding transfers of data between the second buffers and the base memory through the first buffer.

Multiple parallel digital data stream channel controller

A multiple data stream channel controller providing demand driven transport of multiple data streams concurrently in real time through a peripheral data channel coupled between a general purpose processor system and a special purpose processor system. The controller comprises a first bus master interface coupleable to a general purpose processor system bus, a second bus master interface coupleable to a special purpose processor system bus, a segmentable buffer memory and a controller that directs the transfer of data segments between the first and second bus master interfaces via the segmentable buffer memory. The controller is responsive to a plurality of signals provided by the special purpose processor bus to request transfer of successive data segments from a respective plurality of data streams staged in the segmentable buffer memory. The controller moderates the transfer of successive data segments of the respective plurality of data streams via the first bus master interface to the segmentable buffer memory.

Multiple parallel digital data stream channel controller architecture

A data transfer control system including a pool memory, a plurality of peripheral devices, and a transfer controller. The pool memory provides for the storage of data in a plurality of FIFOs formed within the pool memory. The plurality of peripheral devices are coupleable to the pool memory to provide for the transfer of data between programmatically associated FIFOs and peripheral devices. The transfer controller is coupled to the pool memory and to the peripheral devices for selectively managing the transfer of data between the FIFOs and the peripheral devices. The transfer controller includes a distributed signaling system coupled to the peripheral devices to permit the broadcast of status information reflective of a transfer of data relative to a predetermined FIFO to the peripheral devices.

System for managing the transfer of data between FIFOs within pool

A bus transfer control system manages the transfer of multiple asynchronous data streams through a buffer pool. The bus transfer control system includes a buffer pool having a plurality of memory blocks, wherein each memory block provides for the storage of a plurality of data bytes and a plurality of data transfer devices coupled to the buffer pool to allow the transfer of segments of one or more data streams to be transferred between the plurality of data tranfer devices through the buffer pool. A transfer controller maintains status information relating to the status of data in the memory blocks and includes control logic for repeatedly evaluating the status information and providing for the prioritied selection of a first data transfer device and a predetermined one of the memory blocks.

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Saratoga, CA, United States of America

Thomas E Kilbourn