3Dlabs Inc., Ltd.

3M Innovative Properties Company

Thomas E Dewey

Phillip Angelo Bolea

Thomas J Brace

Fusu Thao

Michele A Waldner

Brian M Kelleher

Giuseppe M Bommarito

Stephen R Alexander

Kathleen M Stenersen

Beth A Fritcher

A scalable graphics processor architecture is disclosed in accordance with the present invention. In a first aspect, the architecture comprises a base graphics architecture. The architecture further includes an expansion graphic architecture, the expansion graphics architecture being mateably coupled to the base graphics architecture. In a second aspect, the architecture comprises a plurality of rendering processors, a first bus coupled to the plurality of processors for providing I/O signals to the processors; and a plurality of digital to analog converters (VDACs). In this aspect, each of the VDACs are adapted for driving a display. The architecture further includes a second bus coupled between the plurality of rendering processors and the plurality of VDACs for providing image data therebetween; and a switch, coupled to a plurality of processors. The switch selectively drives the rendering processors such that one of the plurality of the VDACs are driven by all of the rendering processors when the switch is in a first mode and the rendering processors drive all of the plurality of VDACs when the switch is in a second mode. Through the use of this architecture, the graphics processor system is expandable to allow more rendering processors to be added as well as allowing the processors to drive multiple VDACs or drive a single VDAC together.

Scalable graphics processor architecture

Growing community of inventors

Redwood City, CA, United States of America

Thomas E Dewey