Intel Corporation

Thomas E Bleakley

Tony M Tarango

A system and method provide a pulse train clock signal having a portion appropriate for loading and loading a scan chain of a circuit under test, and a higher frequency portion with a sharp leading edge appropriate for inputting a test signal into the scan elements for transition fault testing. Embodiments provide this signal by taking as inputs to a multiplexer switch, two synchronous pulse trains, and provide edge sharpening and frequency raising to one of the signals, and input each of these signals into a multiplexer switch, and rapidly switch between these signals depending upon a selection control signal that is synchronous with each signal. The multiplexer switches between these input signals during a low valued portion of each signal so that the less sharp edge of the selection control signals and the high frequency input signal do not affect the sharp pulse of the very high frequency portion.

Circuit for producing a variable frequency clock signal having a high frequency low jitter pulse component

Embodiments of the present invention include first and second pulse trains input to a switch in synchronization. The first and second pulse trains may have a repeating high and low values at first and second frequencies, respectively, and the first pulse train may transition from the low to the high value with a first edge sharpness. The second pulse train input may have a lower than the first frequency. The switch may use a selection signal in synchronization with the first pulse train to select an output from the first or second pulse train to create an output pulse train appropriate to transition fault test an integrated circuit. The switch may switch from the second pulse train to the first pulse train and substantially maintain the first edge sharpness of the first pulse train during a low value of both the first and second pulse trains.

Embodiments of the invention relate to techniques for automatic degradation testing of a high-speed serial receiver. A transmitter manipulator couples to a transmitter of a serial interface circuit. The transmitter is coupled to the receiver of the serial interface circuit. The transmitter manipulator includes a storage to store one of current compensation values or impedance compensation values and sequencing logic to dynamically sequence the one of the current compensation values or impedance compensation values to the transmitter. The transmitter responsive to the dynamically sequenced one of the current or impedance compensation values generates a degraded test pattern signal to transmit to the receiver in order to test the receiver.

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El Dorado Hills, CA, United States of America

Thomas E Bleakley