Texas Instruments Corporation

Thomas Dyer Bonifield

Jeffrey Alan West

Byron Lovell Williams

Elizabeth Costner Stewart

Peijun Chen

Duofeng Yue

Sue E Crank

Shrinivasan Jaganathan

Amitabh Jain

Anant Shankar Kamath

Masood Murtuza

Satyendra Singh Chauhan

Rajiv Carl Dunne

John Kenneth Arch

Gary Paul Morrison

Raja Selvaraj

Homi C Mogul

Scott Robert Summerfelt

Honglin Guo

James Carl Baker

David Leonard Larkin

Douglas E Paradis

Dhaval Atul Saraiya

Julie S England

Emily A Groves

Barry Lanier

Jay Sung Chun

Charles P Monaghan

Zhiyi Yu

Benjamin Stassen Cook

Swaminathan Sankaran

William David French

Peter Smeys

Anindya Poddar

Jiong-Ping Lu

Monte A Douglas

Ricky A Jackson

Dok Won Lee

Neil Gibson

Brian Goodlin

Woochan Kim

Vivek Kishorechand Arora

Rhett B Jucha

Erika Lynn Mazotti

Mikhail Valeryevich Ivanov

Andrew J Purdes

Sreeram Subramanyam Nasum

Tobias Bernhard Fritz

Basab Chatterjee

Maxim James Franke

Byron J R Shulver

Mrinal Kanti Das

Glenn A Cerny

Yoshihiro Takei

Klaas De Haan

Joseph Andre Gallegos

Cecil J Davis

William R McKee

Gregory C Smith

Mona M Eissa

Robert Yung-Hsi Tsu

Asad Mahmood Haider

Joe W McPherson

John E Spencer

Vladimir Ukraintsev

William Robert Morrison

John I Jones

Randall E Johnson

Rajesh Tiwari

Jeff A West

Vic B Marriott

Adrian Salinas

Roc Blumenthal

Dennis J Yost

Scott Alexander Johannesmeyer

David Permana

Dhanoop Varghese

Thomas W Winter

Kannan Soundarapandian

William J Stiltz

Joseph E Whetsel

Toshiyuki Tamura

Young Sawk Oh

Gregory D Winterton

Jie-Jie Xu

Albert Cheng

Mitsuhiro Sugimoto

Brock W Fairchild

Chris M Bowles

An integrated circuit includes a first isolation capacitor and a second isolation capacitor. The first isolation capacitor is electrically connected to a first circuit node and has first and second capacitor plates separated by a first dielectric stack. The second isolation capacitor is electrically connected in series between the first isolation capacitor and a second circuit node, and includes third and fourth capacitor plates separated by a second dielectric stack different from the first dielectric stack.

Hybrid isolation capacitors in series

An integrated circuit (IC) package includes a first die with a first surface overlaying a substrate. The first die includes a first metal pad at a second surface opposing the first surface. The IC package also includes a dielectric layer having a first surface contacting the second surface of the first die. The IC package further includes a second die with a surface that contacts a second surface of the dielectric layer. The second die includes a second metal pad aligned with the first metal pad of the first die. A plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.

IC package with multiple dies

Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

High voltage flip-chip on lead (FOL) package

A microelectronic device including an isolation device. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The inorganic dielectric plateau contains an upper etch stop layer and a lower etch stop layer between the upper isolation element and the lower isolation element. The upper etch stop layer provides an end point signal during the plateau etch process which provides feedback on the amount of inorganic dielectric plateau which has been etched. The lower etch stop layer provides a traditional etch stop function to provide for a complete plateau etch and protection of an underlying metal bond pad. The inorganic dielectric plateau also contains alternating layers of high stress and low stress silicon dioxide, which provide a means of reinforcement of the inorganic dielectric plateau.

Single die reinforced galvanic isolation device

An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

Standalone isolation capacitor

A semiconductor device can include first and second conductive layers that can be positioned over a substrate, and at least one dielectric layer between the first and second conductive layers. The at least one dielectric layer can be positioned over at least a portion of the second conductive layer, and the first conductive layer can be positioned over a portion of the least one dielectric layer. The semiconductor device can further include a third conductive layer that can be positioned over the substrate and can be conductively connected to the second conductive layer and the substrate. The third conductive layer includes a fusible link.

Isolation device with safety fuse

A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

Standalone high voltage galvanic isolation capacitors

In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

Through wafer trench isolation between transistors in an integrated circuit

An electronic device has a substrate and first and second metallization levels with a resonant circuit. The first metallization level has a first dielectric layer on a side of the substrate, and a first metal layer on the first dielectric layer. The second metallization level has a second dielectric layer on the first dielectric layer and the first metal layer, and a second metal layer on the second dielectric layer. The electronic device includes a first plate in the first metal layer, and a second plate spaced apart from the first plate in the second metal layer to form a capacitor. The electronic device includes a winding in one of the first or second metal layers and coupled to one of the first or second plates in a resonant circuit.

Resonant inductive-capacitive isolated data channel

An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

IC including capacitor having segmented bottom plate

An isolator device includes a laminate die having a dielectric laminate material with a metal laminate layer on one side of the dielectric laminate material, the metal laminate layer being a patterned layer providing at least a first plate, including a dielectric layer over the first plate that includes an aperture exposing a portion of the first plate. An integrated circuit (IC) including a substrate having a semiconductor surface includes circuitry including a transmitter and/or a receiver, the IC including a top metal layer providing at least a second plate coupled to a node in the circuitry, with at least one passivation layer on the top metal layer. A non-conductive die attach (NCDA) material for attaching a side of the dielectric laminate material is opposite the metal laminate layer to the IC so that the first plate is at least partially over the second plate to provide a capacitor.

Laminate stacked on die for high voltage isolation capacitor

An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.

High performance high voltage isolators

Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

Device isolator with reduced parasitic capacitance

An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.

Integrated capacitor with sidewall having reduced roughness

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Dallas, TX, United States of America

Thomas Dyer Bonifield