Cypress Semiconductor Corporation

Thomas Davenport

Shan Sun

John Edward Cronin

Donald J Verhaeghe

Robert Sommervold

Krishnaswamy Ramkumar

Ali Keshavarzi

Fan Chu

Alan D DeVilbiss

Thurman John Rodgers

Kedar Patel

A microelectronic system including hydrogen barriers and copper pillars for wafer level packaging and method of fabricating the same are provided. Generally, the method includes: forming an insulating hydrogen barrier over a surface of a first chip; exposing at least a portion of an electrical contact electrically coupled to a component in the first chip by removing a portion of the insulating hydrogen barrier, the component including a material susceptible to degradation by hydrogen; forming a conducting hydrogen barrier over at least the exposed portion of the electrical contact; and forming a copper pillar over the conducting hydrogen barrier. In one embodiment, the material susceptible to degradation is lead zirconate titanate (PZT) and the microelectronic systems device is a ferroelectric random access memory including a ferroelectric capacitor with a PZT ferroelectric layer. Other embodiments are also disclosed.

Hydrogen barriers in a copper interconnect process

Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS transistor. A local interconnect (LI) layer is deposited over the top surface of the first dielectric layer and the first contact, a ferro stack including a bottom electrode, a top electrode and ferroelectric layer there between deposited over the LI layer, and the ferro stack and the LI layer patterned to form a ferroelectric capacitor and a LI through which the bottom electrode is electrically coupled to the diffusion region of the MOS transistor.

Methods of fabricating an F-RAM

An apparatus that includes a reference generating circuit configured to generate a reference signal for a non-volatile memory (NVM) device, the reference generating circuit including a first circuit comprising at least one metal-oxide-semiconductor capacitor, the first circuit generating a first signal component of the reference signal, and a second circuit comprising at least one ferroelectric capacitor, the second circuit generating a second signal component of the reference signal, in which the second signal component is temperature dependent.

Hybrid reference generation for ferroelectric random access memory

A method for a non-volatile, ferroelectric random access memory (F-RAM) device that includes a ferroelectric capacitor aligned with a preexisting structure is described. In one embodiment, the method includes forming an opening in an insulating layer over a contact in a planar surface of a substrate to expose at least a portion of the contact. Next a self-aligned contact (SAC) is formed electrically coupling to the contact, the SAC medially located in the opening and proximal to a sidewall thereof. A ferroelectric spacer is then formed in the opening medially of the SAC, and a top electrode spacer formed in the opening over the insulating cap and medially of the ferroelectric spacer.

Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) having a ferroelectric capacitor aligned with a three dimensional transistor structure

A method of minimizing imprint in a ferroelectric capacitor uses a gradually attenuated AC field to electrically depolarize the ferroelectric capacitor before being packaged. The AC field is linearly attenuated, and generated using a series of voltage pulses, down to a minimum allowed voltage. A final pulse is a positive voltage to minimize hydrogen degradation during packaging. Thermal depoling can also be used.

Method minimizing imprint through packaging of F-RAM

Disclosed herein is an apparatus that includes a ferrocapacitor having a sidewall. An etch stopping film is disposed along the sidewall of the ferrocapacitor, with a hydrogen barrier film disposed between the etch stopping film and the sidewall of the ferrocapacitor.

Eliminating shorting between ferroelectric capacitors and metal contacts during ferroelectric random access memory fabrication

A method of encapsulating a ferroelectric capacitor or ferroelectric memory cell includes forming encapsulation materials adjacent to a ferroelectric capacitor. forming a ferroelectric oxide (FEO) layer over the encapsulated ferroelectric capacitor, and forming an FEO encapsulation layer over the ferroelectric oxide to provide additional protection from hydrogen induced degradation.

Enhanced hydrogen barrier encapsulation method for the control of hydrogen induced degradation of ferroelectric capacitors in an F-RAM process

A method for improving data retention in a 2T/2C ferroelectric memory includes baking a ferroelectric memory configured to operate as an array of 1T/1C memory cells for a period of time, and then configuring the ferroelectric memory to function as an array of 2T/2C memory cells, wherein the baking pre-imprints the ferroelectric capacitors in the ferroelectric memory and stabilizes a 2T/2C opposite state margin and enhances data retention. A corresponding memory circuit for configuring an array of memory cells for either 1T/1C operation or 2T/2C operation includes a plurality of sense amplifiers, a configurable reference circuit coupled to a logic circuit, a memory array, and a column decoder, wherein components are coupled together through a bit line and a complementary bit line, and wherein the logic circuit can configure the reference circuit for 1T/1C operation or 2T/2C operation.

Method for improving data retention in a 2T/2C ferroelectric memory

A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate, and forming bottom electrode spacers proximal to sidewalls of the opening. Next, a ferroelectric dielectric layer is formed in the opening over the surface of the substrate and between the bottom electrode spacers, and a pair of top electrodes is formed within the opening comprising first and second side portions displaced laterally from respective ones of the bottom electrode spacers by the ferroelectric dielectric layer.

Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) with simultaneous formation of sidewall ferroelectric capacitors

Disclosed is a novel non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM device structure on a planar surface using a reduced number of masks and etching steps.

Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) device structure employing reduced processing steps

Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.

Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors.

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Denver, CO, United States of America

Thomas Davenport