Cyrix Corporation

Augat Inc.

Thomas D Selgas

Sean T Crowley

Stephen D DelPrete

Donald Santos

Kerry D Arnold

Thomas B Brightman

William C Patton

Stanley D Harder

Paul J Pascarelli

Antonio Savarese

The present invention comprises a system for monitoring the angular movement of a structure's foundation, wall, beam and/or column with one or more monitoring devices in communication with either a local computing device (a hub) that displays the current angular deviation and direction from an initialized state, a remote server capable of generating a web page display of the current angular deviation and direction from an initialized state, or both. Additionally, the hub can be connected to the internet where data from the monitoring devices it is in communication with can be shared with a remote monitoring service, off-site server or both.

Foundation monitoring system

A method of data communication between asynchronous processes of a computer system is disclosed in connection with a cache coherency system for a processor-cache used in a multi-master computer system in which bus arbitration signals either are not available to the processor-cache, or are not exclusively relied on by the processor-cache to assure validity of the data in the cache (e.g., a 386-bus compatible computer system using an external secondary cache in which bus arbitration signals are only connected to and used by the secondary cache controller). In an exemplary external-chip implementation, the cache coherency system (120) comprises two PLAs--a FLUSH module (122) and a WAVESHAPING module (124). The FLUSH module (a) receives selected bus cycle definition and control signals from a microprocessor ((110), (b) detects FLUSH (cache invalidation) conditions, i.e., bus master synchronization events, and for each such FLUSH condition, (c) provides a FLUSH output signal. The WAVESHAPING module provides a corresponding CPU/FLUSH signal to the microprocessor with the appropriate set up and hold time. The exemplary bus master synchronization events, or FLUSH conditions, that cause cache invalidation are: (a) hardware generated interrupts, and (b) read or read/write accesses to I/O address space, except for those directed to a hard disk or an external coprocessor. If the bus architecture uses memory-mapped I/O, accesses to selected regions of memory-mapped I/O space could also be used. The cache coherency functionality could be implemented on-board the microprocessor.

Cache coherency without bus master arbitration signals

An integrated circuit extraction tool for extracting sockets or microprocessors having a staggered pin grid array (SPGA) pin arrangement. Such tool includes an elongated base having a first end and a second end, each end forming a set of teeth that permit entry and extension of the teeth, diagonally, through the staggered pins of the socket or microprocessor. In the preferred embodiment, the first end is disposed at ninety degree with respect to the elongated base. Further, the elongated base is formed with a curvature to enhance the leverage action necessary for an extraction operation.

Integrated circuit extraction tool

An integrated circuit extraction tool includes an elongated base having a first end and second end. A first set of teeth are provided on the first end and a second set of teeth are provided on the second end. The first set of teeth are spaced at a first spacing distance and the second set of teeth are spaced at a second spacing distance. In the preferred embodiment, the first set of teeth are spaced to correspond with the spacing between pins of a integrated circuit to be extracted and the second set of teeth are spaced at a distance to correspond to the spacing between base portions of a socket's connectors. One or both of the ends may be angled at ninety degrees to allow integrated circuit removal with minimal clearance.

A component carrier and mating system is disclosed for aligning and mating closely spaced leads of integrated circuit (IC) packages, which protects the integrated circuit packages and permits easy installation. The system is particularly adapted for aligning and mating integrated circuits which have high pin counts. A carrier assembly aligns for mating and interconnecting at least two integrated circuit packages having a plurality of leads extending from the packages. A protective shroud covers the stacked packages to maintain the packages in electrical and mechanical engagement and to assure that no damage occurs to the integrated circuit packages. In one embodiment, a first package is installed on the carrier assembly and coupled with the protective shroud to form a pre-engagement assembly, the pre-engagement assembly is then engaged with a second package mounted on a printed circuit board. An extraction tool facilitates disengagement of the assembly from the second package mounted on the printed circuit board.

Growing community of inventors

Garland, TX, United States of America

Thomas D Selgas