Hewlett-packard Development Company, L.P.

Hewlett Packard Enterprise Development LP

Thomas D Rhodes

Wade David Vinson

Peter A Hansen

Alex Olson

John P Franz

Paul R Culley

David F Heinrich

Andrew Brown

Montgomery C McGraw

Reza Mushtag Bacchus

Andrew C Cartes

Binh Nguyen

Jay C Brinkmeyer

Christoph L Schmitz

Stephen Kay

Huong Truong

Long B Sam

Kurt A Manweiler

Timothy Majni

Nicholas Mark Hawkins

Wayne Hsu

A technique includes monitoring a sequence of bits of data communicated to a transmitter of a node, where the transmitter communicates signals with a bus in response to the sequence of bits. The technique includes determining whether the sequence of bits represents acknowledgement by the node that data was received from the bus in an associated data frame and represents detection by the node of an error associated with the data frame. The technique includes detecting a fault associated with the bus based on the result of the determination.

Detecting bus faults

A converged infrastructure manager comprises a circuit board, a processor connected to a first side of the circuit board, a solid state drive connected to the circuit board, a first connector extending from the first side of the circuit board, a second connector extending from a second side of the circuit board, a first dual in-line memory module connected to the first connector and a second dual in-line memory module connected to the second connector.

Converged infrastructure manager

An example device may include processing circuitry and a management controller. The processing circuitry may include a communications interface that includes a first register and a second register. The first register may include a freshness bit and a number of first data bits. The second register may include a number of second data bits that correspond, respectively, to the first data bits. The processing circuitry may write variously to the first data bits in response to detected events, set the freshness bit in response to the management controller reading the first data bits, and reset the freshness bit if any of the first data bits are written to. The management controller may read the first data bits, perform predetermined processing based thereon, write to the second data bits based on the predetermined processing, and request a register transfer. The processing circuitry may, in response to the management controller requesting the register transfer, transfer values of the second data bits to their respectively corresponding first data bits if and only if the freshness bit is currently asserted.

Register-based communications interface

An intelligent air moving apparatus for cooling an electronics enclosure includes a motor for driving a fan at a variable rotational speed and a microcontroller for controlling the rotational speed of the motor. The microcontroller includes a speed sensor for sensing the rotational speed such that when the sensed rotational speed deviates below a target speed, the microcontroller detects a locked rotor condition.

Intelligent air moving apparatus

A computer-implemented method is used for determining cooling requirements of a computer system enclosure, where the enclosure includes a number of installed modules, the modules including fan modules. The method includes the steps of determining an individual impedance curve of each installed module; determining fan curves for the installed fan modules; based on the individual impedance curves, determining an overall system impedance curve for the computer system; determining desired performance requirements for the computer system; based on the desired performance requirements, determining corresponding fan curves; and choosing a fan curve that intersects the system impedance curve.

Method for determining cooling requirements of a computer system enclosure

Systems and methods for updating at least one field replaceable unit (FRU) are disclosed. In an exemplary embodiment the method may comprise generating a virtual image of a FRU ID for each FRU to be updated. The method may also comprise storing the virtual image separate from the FRU ID. The method may also comprise providing a handle to the virtual image so that updated information is retrieved from the virtual image when the FRU is accessed.

Systems and methods for updating field replaceable units

In at least some embodiments, a system comprises a processor and a memory coupled to the processor. The memory stores processor performance utility instructions and performance adjustment instructions. When executed, the processor performance utility instructions are configured to cause activities of the processor to be counted and to cause a processor utilization value to be determined based on the counts. When executed, the performance adjustment instructions are configured to adjust the processor utilization value based on a comparison of the processor's current operating frequency and maximum operating frequency.

Systems and methods to determine processor utilization

A method to communicate provide server management information that emulates a floppy disk drive (FDD) with a management processor. This management processor operably couples to a multi-function integrated circuit having a FDD controller. Monitoring hardware and sensors operably couple to the management processor and write server management information to data files within the emulated FDD. Programs that utilize the server management information may then read this server management information.

Growing community of inventors

The Woodlands, TX, United States of America

Thomas D Rhodes