Harris Corporation

Other

Thomas D Housten

Salomon Vulih

John A Olmstead

Stanley F Wietecha

George R Briggs

A circuit for generating a bandgap voltage that is insensitive to temperature. The circuit includes an amplifier with a feedback loop having a high impedance output current mirror controlled by transistors connected to an output from the amplifier. The current mirror provides proportional currents to a pair of resistors that are connected to inputs to the amplifier, a first input receiving a temperature sensitive voltage from a first of the resistors, and a second input receiving a voltage that is a combination of a temperature sensitive voltage across a second of the resistors and a temperature sensitive offsetting voltage. The second resistor may be tapped to provide a selectable bandgap voltage. A reference voltage for operating the generator may be obtained from a voltage division of supply voltage by two resistors of the same type.

Temperature insensitive bandgap voltage generator tracking power supply

A circuit for providing an input offset voltage to balance a fully differential amplifier may include two field effect transistors (FETs) in parallel conductive paths for receiving a current, an amplifier current source, a resistor connecting the FETs at their drains, and a second amplifier with inputs for an offset correction voltage and for a reference voltage on which the fully differential amplifier is to be balanced and outputs for providing control inputs to the FETs. The input offset voltage for balancing the fully differential amplifier is the difference between currents in the parallel paths times the resistance of the resistor. The circuit may be used to balance a fully differential amplifier in a telephone CODEC. The correction voltage may correct the total offset from the CODEC, or the offset introduced by a sign bit integrator that provides a correction for excursions of the same polarity in the CODEC.

Offset adjustment for fully differential amplifiers

A telephone system coder/decoder (CODEC) having improved access for testing CODEC components and a method of testing a CODEC in which a test signal is not contaminated by passage through CODEC filters. Input test pads are positioned between the receive channel filters and the connection of the receive channel to the hybrid balance network, and an output test pad is positioned between the transmit channel filters and the connection of the transmit channel to the hybrid balance network. Test signals selectively applied to the test pads or to CODEC terminals indicate operation of receive programmable gain section, hybrid balance network frequency response, hybrid balance network echo cancellation, and the transmit buffer, buffer splitter and transmit programmable gain section in the transmit channel. The test signals do not go through the transmit and receive filters.

Testing circuit and method for a codec hybrid balance network

Methods of increasing the number of possible network configurations available during the manufacture of an integrated circuit hybrid balance network containing a fixed number of selectable network configurations in the manufactured network by including a network element selection layer programmable during the manufacturing process. The programming may be accomplished using ROM matrices programmed during or subsequent to the manufacturing process, or alternatively may be accomplished by the programming of the metal masks interconnecting the semiconductor portions of the IC without the necessity for changing the semiconductor masks.

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Somerville, NJ, United States of America

Thomas D Housten