Intel Corporation

North American Philips Corporation

North American Philips Corp, Signetics Division

North American Philips Corp., Signetics Div.

Intel Corporatoin

Thomas D Fletcher

Jesus Corbal

Dennis Ryan Bradford

Robert Valentine

Mark Jay Charney

Edward Thomas Grochowski

Brian J Hickmann

Glenn J Hinton

David J Sager

Michael D Upton

Javed Sabir Barkatullah

Warren E Ferguson

Gilbert A Neiger

Rajesh M Sankaran

Eriko Nurvitadhi

Milind Baburao Girkar

Koichi Yamada

Joseph Nuzman

Deborah T Marr

Stephen R Van Doren

Terry I Chappell

Lokpraveen B Mosur

Paul Caprioli

Narayan Ranganathan

Kent D Glossop

Niall D McDonnell

Jonathan D Pearce

Richard J Greco

Jeffrey J Cook

Ganesh Venkatesh

Asit K Mishra

Dwight P Manley

David B Sheffield

Tracy Garrett Drysdale

Mark S Milshtein

Nicholas P Carter

Edward A Burton

Roman S Dubtsov

Michael A O'Hanlon

Nikita A Shustrov

Eitan E Rosen

Kevin X Zhang

Andrew Thomas Forsyth

Susan Julia Corwin

Amit Gradstein

Feng Chen

Xia Dai

Roger Espasa

Giao N Pham

Lisa K Wu

Milo D Sprague

David J Kaplan

Alex Pineiro

Simon Rubanovich

Benny Eitan

Wei Wu

Shantanu R Gupta

Eric A Sprangle

Sorin Iacobovici

Barbara A Chappell

Douglas M Carmean

Mandar S Joshi

Paul D Madland

Jonathan Cannon Hall

Dror Markovich

Shahram Jamshidi

Timothy S Beatty

Charles E Dike

Guillem Sole

Jose-Alejandro Pineiro

Kumar A Anshumali

Yong-In Shin

Manel Fernandez

Christopher P McAllister

Kevin (Xia) Dai

Rommel O Dizon

Emil N Hahn

Benny T Ma

Niall D Mcdonnell

Michael A O'HANLON

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

Embodiments of systems, apparatuses, and methods for chained fused multiply add. In some embodiments, an apparatus includes a decoder to decode a single instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of packed data source operands of a first type that have packed data elements of a first size, a second source field representing a plurality of packed data source operands that have packed data elements of a second size, and a field for a memory location that stores a scalar value. A register file having a plurality of packed data registers includes registers for the plurality of packed data source operands that have packed data elements of a first size, the source operands that have packed data elements of a second size, and the destination operand. Execution circuitry executes the decoded single instruction to perform iterations of packed fused multiply accumulate operations by multiplying packed data elements of the sources of the first type by sub-elements of the scalar value, and adding results of these multiplications to an initial value in a first iteration and a result from a previous iteration in subsequent iterations.

Systems, apparatuses, and methods for chained fused multiply add

A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on multiple data elements stored in a storage location indicated by a first source operand. The instruction schedule/dispatch unit is to determine a first of the data elements that will not be operated to generate a result written to a destination operand based on a second source operand. The processor further includes multiple processing elements coupled to the instruction schedule/dispatch unit to process the data elements of the SIMD instruction in a vector manner, and a power management unit coupled to the instruction schedule/dispatch unit to reduce power consumption of a first of the processing elements configured to process the first data element.

Vector mask driven clock gating for power efficiency of a processor

A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.

Super multiply add (super MADD) instructions with three scalar terms

Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a set of vector registers, a size of each of the vector elements, a portion of the vector elements upon which to compute linear interpolations, a second operand from a set of vector registers, and a third operand; an execution unit, reads a first, a second and a third value of the size of vector elements from corresponding data fields in the first, the second and the third operand respectively and computes an interpolated value as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value.

Instruction and logic to provide vector linear interpolation functionality

A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.

Super multiply add (super madd) instruction

Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome.

Consecutive bit error detection and correction

A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to CCXCX. The functional unit has a multiplier circuit. The multiplier circuit has: i) a first input to receive bits of a first operand of the first instruction and receive bits of a Cterm of the second instruction; ii) a second input to receive bits of a second operand of the first instruction and receive bits of a Xterm of the second instruction.

Functional unit capable of executing approximations of functions

A processor includes a front end with logic to identify a multiplier, multiplicand, and mathematical mode based upon an instruction. The processor also includes a multiplier circuit to apply Booth encoding to multiply the multiplier and multiplicand. The multiplier circuit includes circuitry to determine leftmost and rightmost partial products of multiplying the multiplier and multiplicand using Booth encoding. The circuitry includes a most significant bit (MSB) array and least significant bit (LSB) array corresponding to the multiplier. The multiplier circuit also includes logic to selectively enable selectors of the circuitry to find partial products based upon the mathematical mode of the instruction.

Instruction and logic for multiplier selectors for merging math functions

Growing community of inventors

Sherwood, OR, United States of America

Thomas D Fletcher