Freescale Semiconductor,inc.

Lattice Semiconductor Corporation

Nxp Usa, Inc.

Thomas D Cook

Jeffrey C Cunningham

Karthik Ramanan

Tahmina Akhter

Ronald J Syzdek

Stephen F McGinty

Frederic Deboes

An exponential multistage charge pump is provided wherein node voltages in a pumpcell in one stage of the charge pump are used to control operation of clock drivers in a subsequent stage of the charge pump.

Exponential charge pump

A charge pump includes a first counter and a pump stage. The first counter has a control input for receiving a control signal, and an output for providing a first count value. The first count value is incremented in response to the control signal being a first logic state and the first count value is decremented in response to the control signal being a second logic state. The pump stage has a variable capacitor. The variable capacitor has a control input coupled to the output of the first counter for receiving the first count value. The capacitance value of the variable capacitor is changed in response to the first count value changing. The capacitance value is for determining a ramp-up rate of an output voltage at an output of the charge pump.

Charge pump having ramp rate control

A method and memory are provided for determining a read reference level for a plurality of non-volatile memory cells. The method includes: performing a program operation of the plurality of non-volatile memory cells; determining a program level of a least programmed memory cell of the plurality of memory cells; performing an erase operation of the plurality of non-volatile memory cells; determining an erase level of a least erased memory cell of the plurality of memory cells; determining an operating window between the program level and the erase level; and setting the read reference level to be a predetermined offset from the erase level if the operating window is determined to compare favorably to a predetermined value. The memory includes registers for storing the program level and the erase level.

Read conditions for a non-volatile memory (NVM)

A target circuit of an electronic device is placed in a suspended mode by disconnecting the target circuit from one or more voltage sources. A refresh controller periodically initiates a refresh operation during the suspended mode by temporarily reconnecting the target circuit to the one or more voltage sources for a duration sufficient to recharge capacitances of the target circuit. The refresh controller terminates the refresh operation by disconnecting the target circuit from the one or more voltage sources, thereby continuing the suspended mode of the electronic device. The refresh controller can employ a Very Low Frequency Oscillator (VLFO) to time the frequency of refresh operations. The VLFO manages the refresh initialization timing based on the voltage across a capacitor that is selectively charged or discharged so as to implement the refresh operation. The refresh controller further can employ a counter to time the duration of the refresh operation.

Refresh operation during low power mode configuration

A charge pump has circuitry and implements a method for monitoring a synchronous load by using a first voltage threshold below a target output voltage and a second voltage threshold above a target output voltage. An output terminal is coupled to the load. Charge is demanded by clocking the load. When the target output voltage passes below the first voltage threshold, a first value representing a present size of a charging capacitance is stored as a stored first value, and a second stored value representing a needed changed size of the charging capacitance is used. The present size of the charging capacitance is changed in response to the passing of the target output voltage below the first voltage threshold. When demand for charge from the load is reduced, a present value is saved and a prior value is restored to change the size of the charging capacitance.

Charge pump for use with a synchronous load

A device for providing a constant output voltage based on a variable input voltage is provided. The device may include: (1) a charge-pump comprising a plurality of cells, wherein each of the plurality of cells can be configured as an input cell, a stepping cell, or a load cell; (2) a comparator; and (3) a differentiator coupled to the comparator output, wherein the differentiator is configured to monitor the comparator output and produce a reset pulse each time the comparator output changes its state. The device may further include: (1) a decimator; (2) an up/down counter; and (3) a controller for detecting whether the device is operating in a first predetermined mode or a second predetermined mode, wherein the two modes relate to the configuration of the plurality of cells into the input cell, the stepping cell, and/or the load cell.

Variable input voltage charge pump

A charge pump and method for starting up a charge pump are provided. The charge pump comprises a plurality of charge pump cells and a start-up control circuit. Each charge pump cell has a clock terminal for receiving a delayed clock signal, an input terminal for receiving an input voltage, and an output terminal for providing a boosted voltage in response to receiving the clock signal and the input voltage. The start-up control circuit is coupled to the clock terminals of each of the plurality of charge pump cells. The start-up control circuit is for delaying the delayed clock signal provided to each charge pump cell of the plurality of charge pump cells. Each of the charge pump cells receives the delayed clock signal having a different predetermined delay so that each of the plurality of charge pump cells are enabled in a predetermined sequence during start-up of the charge pump.

Low power charge pump and method of operation

A charge pump charges a first capacitor to a predetermined input voltage using a first switch. The first switch is coupled to a first terminal of the first capacitor for coupling the first terminal to an input terminal that receives the predetermined input voltage. A second switch couples a second terminal of the first capacitor to a reference voltage terminal. Charge is sequentially transferred from the first capacitor to an output capacitance by using the first switch. A portion of charge is sequentially removed from the output capacitance to the input terminal using a third switch and a second capacitor. Configuration logic provides control signals to make one or more of a plurality of charge transfer capacitors switch the same as said first capacitor switches.

Charge pump with charge feedback and method of operation

A charge-based voltage multiplier device comprising a charge-pump circuit and a charge-pump controller is provided. The charge-pump circuit is configured to multiply an input voltage signal (V) into an output voltage signal (V), the charge-pump circuit includes a plurality of charge-pump stages, wherein at least one of the charge-pump stages includes a weighted capacitor array of pump cells. The charge-pump controller is configured to provide a pump cell select to selectively control the weighted capacitor array of pump cells of the at least one of the charge-pump stages of the charge-pump circuit.

Variable load, variable output charge-based voltage multipliers

A reference voltage regulation circuit () is provided in which one or more input voltage signals (Vref, Vref') are selectively coupled to a configurable amplifier () which is coupled through a sample and hold circuit () to a voltage follower circuit () which is coupled in feedback to the configurable amplifier () for generating an adjusted output voltage at a circuit output (), where the voltage follow circuit comprises a resistor divider circuit () that is controlled by a calibration signal (Cal&#x3c;n:0&#x3e;) generated by a counter circuit () selectively coupled to the output of the configurable amplifier when configured as a comparator for generating the calibration signal in response to a clock signal, where the calibration signal represents a voltage error component (Verror, Voffset) that is removed from the circuit output when the calibration signal is applied to the resistor divider circuit during normal operational.

Built-in self-calibration (BISC) technique for regulation circuits used in non-volatile memory

A level converter comprises first and second latches, and first through fourth transistors. The first latch has first and second power supply terminals, and first and second nodes. The second latch has third and fourth power supply terminals, and third and fourth nodes. The first transistor has a first current electrode coupled to the first node, a control electrode coupled to receive a first bias voltage, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias voltage. The third transistor has a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode. The fourth transistor has a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to receive the second bias voltage, and a second current electrode coupled to the fourth node.

Level shifter

Systems and methods are disclosed herein to provide low pass filters. For example, in accordance with an embodiment of the present invention, a synchronous low pass filter is disclosed. The filter may be employed, for example, to suppress signal transients in power supply monitoring applications.

Growing community of inventors

Austin, TX, United States of America

Thomas D Cook