Spin Memory, Inc.

Integrated Silicon Solution, (cayman) Inc.

Other

Spin Transfer Technologies, Inc.

Thomas D Boone

Mustafa Pinarbasi

Pradeep Manandhar

Bartlomiej Adam Kardasz

Elizabeth Ann Dobisz

Yuan-Tung Chin

Jorge Vasquez

Girish Jagtini

Manfred Ernst Schabes

Jacob Anthony Hernandez

Prachi Shrivastava

Georg Wolf

Pirachi Shrivastava

Girish Jagtiani

A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.

Method for manufacturing a magnetic random-access memory device using post pillar formation annealing

Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; a third terminal is coupled to the second device and a fourth terminal is coupled to the first device, wherein the first terminal and second terminal are independently coupled to the first device and second device respectively. The first terminal, the second terminal, the third terminal and the fourth terminal couple components included in the multi terminal stack to components not included in the multi terminal stack.

Multi terminal device stack systems and methods

Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a multi terminal fabrication process comprises: performing an initial pillar layer formation process to create layers of a multi terminal stack; forming a first device in the layers of the multi terminal stack; forming a second device in the layers of the multi terminal stack; and constructing a set of terminals comprising: a first terminal coupled to the first device, a second terminal coupled to the second device; and a third terminal coupled to the first device; wherein at least two terminals in the set of terminals are independent. The third terminal can be coupled to the second device.

Multi terminal device stack formation methods

Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; and a third terminal is coupled to the first device, wherein the first terminal and second terminal are independently coupled to the first device and second device respectively. The third terminal can be coupled to the second device. The first terminal, the second terminal, and third terminal and couple components included in the multi terminal stack to components not included in the multi terminal stack.

A magnetic random access memory chip having magnetic memory elements with different performance characteristics formed on the same chip. The magnetic memory elements can be magnetic random access memory elements. The memory chip can have a first set of magnetic random access chips having a first set of physical and performance characteristics formed in a first area of the sensor and a second set of magnetic random access chips having a second set of performance characteristics formed in a second area of the chip. For example, the first set of magnetic random access memory elements can have performance characteristics that match or exceed those of a non-volatile memory, whereas the second set of magnetic random access memory elements can have performance characteristic that match or exceed those of a static random access memory element.

Magnetic memory chip having nvm class and SRAM class MRAM elements on the same chip

A method for manufacturing a magnetic memory element structure using a Ru hard mask and a post pillar thermal annealing process. A Ru hard mask is formed over a plurality of memory element layers and an ion milling is performed to transfer the image of the Ru hard mask onto the underlying memory element layers. A high-angle ion milling an be performed to remove any redeposited material from the sides of the memory element layers, and a non-magnetic, dielectric material can be deposited. A thermal annealing process can then be performed to repair any damage caused by the previously performed ion milling processes.

Method for manufacturing magnetic memory element with post pillar formation annealing

A method for manufacturing a magnetic memory element array that includes the use of a Ru hard mask layer and a diamond like carbon hard mask layer formed over the Ru hard mask layer. A plurality of magnetic memory element layers are deposited over a wafer and a Ru hard mask layer is deposited over the plurality of memory element layers. A layer of diamond like carbon is deposited over the Ru hard mask layer, and a photoresist mask is formed over the layer of diamond like carbon. A reactive ion etching is then performed to transfer the image of the photoresist mask onto the diamond like carbon mask, and an ion milling is performed to transfer the image of the patterned diamond like carbon mask onto the underlying Ru hard mask and memory element layers. The diamond like carbon mask can then be removed by reactive ion etching.

Method for manufacturing a magnetic memory element using Ru and diamond like carbon hard masks

Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a semiconductor device comprises: a first pillar magnetic tunnel junction (pMTJ) memory cell that comprises a first pMTJ located in a first level in the semiconductor device; and a second pillar magnetic tunnel junction (pMTJ) memory cell that comprises a second pMTJ located in a second level in the semiconductor device, wherein the second pMTJ location with respect to the first pMTJ is coordinated to comply with a reference pitch for the memory cell. A reference pitch is associated a first switch coupled to the first pMTJ and the second pitch reference component is a second switch coupled to the second pMTJ. The first switch and second switch can be transistors. The reference pitch coordination facilitates reduced pitch between memory cells and increased information storage capacity of bits per memory device area.

Memory device having overlapping magnetic tunnel junctions in compliance with a reference pitch

Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, the method comprises: forming a first pitch reference component and a second pitch reference component; forming a first pillar magnetic tunnel junction (pMTJ) located in a first level and a second pMTJ located in a second level, wherein the location of the second pMTJ with respect to the first pMTJ is coordinated based upon a reference pitch distance between the first pitch reference component and first pitch reference component. In one exemplary implementation, the first pitch reference component is a first switch coupled to the first pMTJ and the second pitch reference component is a second switch coupled to the second pMTJ. The reference component size can be based upon a minimum lithographic processing dimension.

Magnetic tunnel junction (MTJ) fabrication methods and systems

A magnetic data recording element for magnetic random access memory data recording. The magnetic data recording element includes a magnetic tunnel junction element that includes a magnetic reference layer, a magnetic free layer and a non-magnetic barrier layer located between the non-magnetic reference layer and the magnetic free layer. The magnetic free layer includes a layer of Hf that causes the magnetic free layer to have an increased perpendicular magnetic anisotropy. This increased perpendicular magnetic anisotropy improves data retention and increases thermal stability, by preventing the magnetization of the magnetic free layer from inadvertently losing its magnetic orientation.

Perpendicular magnetic tunnel junction retention and endurance improvement

A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.

Process for creating a high density magnetic tunnel junction array test platform

A method for testing individual memory elements or sets of memory elements of an array of magnetic memory elements. The method involves forming a mask such as photoresist mask over an array memory elements. The mask is configured with an opening over each of the selected memory elements to be tested. The mask can be formed of photoresist which can be patterned by focused electron beam exposure to form opening at features sizes smaller than those available using standard photolithographic processes. An electrically conductive material is deposited over the mask and into the openings in the mask to make electrical contact with the selected memory element or memory elements to be tested. Then, electrical connection can be made with the electrically conductive material to test the selected one or more magnetic memory elements.

Method for measuring proximity effect on high density magnetic tunnel junction devices in a magnetic random access memory device

A method for a photolithographic fabricating process to define pillars having small pitch and pillar size. The method includes coating a hard mask layer of a wafer with a photoresist. The wafer is exposed with a first line pattern comprising a plurality of parallel lines in a first direction. The wafer is then exposed with a second line pattern comprising a plurality of parallel lines in a second direction orthogonal to the first direction. The wafer is then developed to remove areas of the photoresist that were exposed by the first line pattern and the second line pattern resulting in a plurality of pillars.

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San Carlos, CA, United States of America

Thomas D Boone