Digital Equipment Corporation

Juniper Networks, Inc.

Compaq Computer Corporation, Inc.

Corero Networks Security, Inc.

Thomas Courtenay Porcher

Oliver Kourosh Tavakoli

Walter Tuvell

Ram Sudama

John W Eng

Jerrold S Leichter

David B Hughes

Robert S DiNitto

Morgan E Robinson

Bruce Eric Mann

Philip John Trasatti

Thomas J Teixeira

Charles S Namias

Tavit K Ohanian

David Vincent Faulkner

Stephen Jay Klein

In a system for detecting and optionally blocking packets from an attacker, an improved multi-hash process, in which rate information for one or more packet signatures is computed by individual modules, where each module corresponds to a different hash function, and is shared across the modules to determine maximum observed rates for the signatures within a specified observation window. A moving average of the maximum rates can be computed across several observation windows, to optimize false negative and false positive detections. The modules may designate certain packets as potentially harmful and/or may block such packets, according to a corresponding maximum rate and specified threshold.

Systems and methods for monitoring and mitigating network attacks

A method may include receiving, in a first server from a second server, a request for a service of a network by a device; sending, from the first server to the second server, a response to the request for the service to permit access to the service; and sending state information about the response to a third server for storage in a database.

High-availability remote-authentication dial-in user service

High-availability Remote-Authentication Dial-In User Service

This disclosure involves the combination of data compression and decompression with a virtual memory system. A number of computer systems are discussed, including so-called embedded systems, in which data is stored in a storage device in a compressed format. In response to a request for data by a central processing unit (CPU), the virtual memory system will first determine if the requested data is present in the portion of main memory that is accessible to the CPU, which also happens to be where decompressed data is stored. If the requested data is not present in the decompressed portion of main memory, but rather is present in a compressed format in the storage device, the data will be transferred into the decompressed portion of main memory through a demand paging operation. During the demand paging operation, the compressed data will be decompressed. Likewise, if data is paged out of the decompressed portion of main memory, and that data must be saved, it can also be compressed before storage in the storage device for compressed data.

Compression of data in read only storage and embedded systems

The invention provides a new and improved system for transferring information between a host system and a terminal system. A digital data processing system includes a host computer system which runs processors and a terminal system which is connected to the application host computer system over a communication link. The terminal system includes one or more virtual terminals each of which allows an operator to enter information and allows output information to be displayed. The association between a terminal device and an application process is a session. Initially, a session is selected by means of a command transferred over the communications link. Thereafter, information, associated with the selected session, may be transferred over the communication link. This may continue until another session is selected. This transfer system minimizes the amount of control information which is required to identify the particular session with which data being transmitted over the communications link is associated. Once a session is selected, it remains selected until another session is selected, after which the data transmitted is associated with the newly selected session.

Terminal device session management protocol

The present invention is circuitry which is employed with a data terminal which data terminal in turn is part of a system including a main data processor. The present circuitry includes a microprocessor which is connected to the main data processor and to the keyboard. The microprocessor processes signals from both the main data processor and the keyboard. The system has a plurality of operational function circuits, such as a circuit to effect smooth scrolling on a data display means. There is logic circuitry connected between the microprocessor and the operational function circuits. The logic circuitry provides a first path which permits signals, generated in response to instructions from the main data processor, to pass therethrough to select one of the operational function circuits and simultaneously therewith to turn the selected circuit either on or off. The logic circuitry also provides a second path which permits signals, generated in response to instructions from the keyboard to pass therethrough to select one of the operational function circuits and turn circuit either on or off. A circuit to generate an impeding signal is also included and is activated by signals from the microprocessor in response to signals from the keyboard. This last mentioned generator circuit is connected to impede signals which would otherwise be transmitted along said first path, whereby said keyboard, after selecting a particular operational function circuit, can 'lock in' that circuit so that the main data processor cannot turn that selected circuit off.

Circuit for selecting and locking in operation function circuitry

The present invention is related to clearing a communication path and in the alternative blocking said communication path between a data terminal and a main data processor, when it appears, from said terminal end, that the data path into the main computer is blocked by some system irregularity in a first case, or should be blocked because of a data overflow condition, in a second case. The present system employs a pair of buffers, the first of which is connected in said communication path, while the second buffer is connected in a data path along which data signals are transmitted from the main data processor. Said communication path includes first logic circuitry connected between said first buffer device and a UART which is connected to the main data processor. Said first logic circuitry can block or unblock the transmission of data to the main data processor. Second logic circuitry is connected between the second buffer and said UART. Said second logic circuitry includes monitoring circuitry which monitors signals coming from the main data processor so that if an 'off' signal is transmitted, then a proper signal will be generated and sent to said first logic circuitry to block data transmission from said terminal.

Signals path control circuitry for a data terminal

The present invention includes a microprocessor which acts to generate groups of its signals from its read only memory (ROM) thereby forming character representations of groups of coded signals, such as ASCII coded signals, coming from a main data processing device. The groups of bit signals are temporarily stored in a buffer which at a subsequent time transmits, in parallel, groups of said bit signals to a bit map memory through some logic circuitry. The group, or block, transfer of said bit signals in parallel, occurs during horizontal or vertical blank periods. The parallel transfer during the blank periods provides part of the basis for acceleration of the data to a display device as compared with the prior art. In addition, the microprocessor provides address information signals to a graphic display controller, which in turn provides starting addresses, for the locations of the bit signals. In addition a bit map memory device is employed to provide pixel information to a CRT display device to create the characters which are to be shown.

Arrangement for providing data signals for a data display system

The present invention is employed in a system which has a bit map memory connected to a CRT display device and the CRT display device can display a fixed region of information and a scrollable region of information. In a preferred embodiment, the system uses a graphic display control circuit to change starting addresses and length ending values of the fixed and scrollable regions in the bit map memory. By changing the starting address one scan line per frame, without any actual transfer of data in memory, from one location to another location, the present system effects a 'smooth' scroll. The system is able to scroll upward and downward. The system uses logic circuitry to load an off screen segment of the bit map memory with additional scrollable information, so that (in an upward scroll load) as a top line of the scrollable information region is no longer displayed, new information will be displayed at the bottom line of said scrollable region. On the other hand during a downward scroll, a bottom line of information on the scrollable region of the screen will fade out and new information is added, from the off screen region, of the bit map memory to provide information for a new top line. In addition the system has the ability to reorganize the information in the bit map memory in the event the size or location of the fixed region is to be altered.

Growing community of inventors

Stow, MA, United States of America

Thomas Courtenay Porcher