Qualcomm Incorporated

Applied Micro Circuits Corporation

Entropic Communications, Inc.

Thomas Clark Bryan

Luverne Ray Peterson

Tin Tin Wee

Alvin Leng Sun Loke

Harry Huy Dang

Stephen Knol

Mark Wayland

Gregory Lynch

Zhixiang Jason Liu

Allen Carl Merrill

Jacob Schneider

Kenneth Dubowski

Reza Jalilizeinali

Yue Li

Mehmet Mustafa Eker

Yu Huang

Wei Li

Stephen Thilenius

Mohammed Mizanur Rahman

Timothy Mowry Hollis

Michael J Brunolli

Wei Fu

Sreen A Raghavan

Ying Duan

Peter J Sallaway

Shih-Wei Chou

Abhay S Dixit

Sreeker Dundigal

Sudhaker Reddy Anumula

Tulsi Manickam

Runhua Sun

Tapan Jyoti Chakraborty

Hong Dai

Hongwen Lu

Scott Powers

Andrew Tohmc

Shuyu Lei

Alvin Loke

Subrahmanya Pradeep Morusupalli

Stewart Webb

Michael Joseph Brunolli

Mark Charles Wayland

Gregory Francis Lynch

Stephen Robert Knol

Duty cycle correction circuits are provided that include a serial combination of a first inverter and a second inverter for inverting an input clock signal into an output clock signal having a corrected duty cycle. The duty cycle correction circuits also include a serial combination of a third inverter and a fourth inverter for inverting a complement input clock signal into a complement output clock signal having a corrected duty cycle.

Fully compensated complementary duty cycle correction circuits

Test architectures for multi-die chips are provided herein according to embodiments of the present disclosure. In certain aspects, an exemplary test architecture enables an external tester to perform various tests on a multi-die chip that includes multiple dies. In a first test mode, the test architecture enables the external tester to currently perform die-level tests on the multiple dies. In a second test mode, the test architecture enables the external tester to perform a chip-level test on the multi-die chip. The chip-level test may include die-to-die tests for testing interconnections between the multiple dies on the multi-die chip. The chip-level test may also include a boundary input/output (I/O) test for testing external connections between the multi-die chip and one or more devices external to the multi-die chip.

Efficient test architecture for multi-die chips

A semiconductor die including: a die-to-die interface including an input/output (I/O) circuitry area and an electrical contact area; wherein the electrical contact area includes an array of electrical contacts disposed on a side of the semiconductor die; and wherein the I/O circuitry area includes a plurality of drivers, each of the drivers coupled to at least one electrical contact in the electrical contact area, and a plurality of electrostatic discharge (ESD) protection devices, each of the ESD protection devices coupled to a respective driver, further wherein the I/O circuitry area and the electrical contact area are separated in a top-down view of the semiconductor die.

Die-to-die interface configuration and methods of use thereof

Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receivesdata bits during operation would havetransceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

Systems and methods for wafer-level loopback test

A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.

Delay line for one shot pre-emphasis

A multi-rank memory bus architecture is provided in which an active DRAM is unterminated and an inactive DRAM terminates to increase the data eye width at the active DRAM.

Termination schemes for multi-rank memory bus architectures

Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

A transmitter is disclosed with a pull-up feedback circuit and a feedback circuit. The transmitter includes an output driver for driving an output terminal.

Transmitter with feedback terminated preemphasis

A programmable equalizer and related method are provided. The equalizer includes a pair of current-setting field effect transistors (FETs) coupled in series with a pair of input FETs and a pair of load resistors, respectively, between a first voltage rail (Vdd) and a second voltage rail (ground). A programmable equalization circuit is coupled between the sources of the input FETs, comprising a plurality of selectable resistive paths and a variable capacitor, which could also be configured as a plurality of selectable capacitive paths. Each of the selectable resistive paths (as well as each of the selectable capacitive paths) include a selection FET for selectively coupling the corresponding resistive (or capacitive) path between the sources of the input FETs. In the case where one of the input FETs is biased with a reference gate voltage, the source of each selection FET is coupled to the source of such input FET.

Programmable high-speed equalizer and related method

A die is provided having an unterminated endpoint that capacitively loads its input impedance with a capacitance from capacitor while acting as a receiving endpoint and that isolates its output impedance from the capacitance while acting as a transmitting endpoint.

Programmable pad capacitance for supporting bidirectional signaling from unterminated endpoints

A circuit includes a data input in communication with a first transistor stack; a first capacitor having a first capacitance and in communication with a power supply via a first transistor of the first transistor stack, wherein the first transistor is configured to charge the first capacitor in response to the data input receiving a signal corresponding to a first binary value; a data output node coupled between the first transistor stack and a transmission line having a second capacitance; and wherein the first capacitor is coupled between the data output node and a second transistor of the first transistor stack, further wherein the second transistor is configured to discharge the first capacitor to the data output node in response to the data input receiving a signal corresponding to a second binary value.

Systems and methods to provide charge sharing at a transmit buffer circuit

Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Systems and methods for clock distribution in a die-to-die interface

Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but for the equalizer.

Circuits and methods providing high-speed data link with equalizer

An input receiver is provided with a pass transistor that is controlled to pass an input signal to an inverter only while a first binary state for the input signal equals a low voltage. The input receiver also includes a source follower transistor configured to pass a threshold-voltage-reduced version of the input signal while the first binary state of the input signal equals a high voltage greater than the low voltage.

Low power receiver with wide input voltage range

Growing community of inventors

San Diego, CA, United States of America

Thomas Clark Bryan