Semiconductor Components Industries, LLC

Marvell International Limited

National Semiconductor Corporation

Thomas Ciccone

Bryan Wayne McCoy

Ajay Karthik Hari

John C Ciccone

Richard Alexander Erhart

Richard David Taylor

Thomas Duffy

Timothy Kaske

In one form, a switched mode power supply controller with frequency foldback includes a pulse width modulator responsive to a clock signal to generate a drive signal having a pulse width that varies in response to a feedback signal, and a variable frequency oscillator having a first input for receiving the feedback signal, a control input for receiving a control signal defining a foldback starting frequency, a foldback ending frequency, a foldback starting voltage, and a foldback ending voltage, and an output for providing the clock signal having a variable frequency that varies over a range between the foldback starting frequency and the foldback ending frequency as the feedback signal varies between the foldback starting voltage and the foldback ending voltage, respectively. The control signal is user programmable for at least one of the foldback starting frequency, the foldback ending frequency, the foldback starting voltage, and the foldback ending voltage.

Switched mode power supply with dynamic frequency foldback

In one form, a switched mode power supply controller with frequency foldback includes a pulse width modulator responsive to a clock signal to generate a drive signal having a pulse width that varies in response to a feedback signal, and a variable frequency oscillator having a first input for receiving the feedback signal, a control input for receiving a programmable control signal defining a foldback starting frequency, a foldback ending frequency, a foldback starting voltage, and a foldback ending voltage, and an output for providing the clock signal having a variable frequency that varies over a range between the foldback starting frequency and the foldback ending frequency as the feedback signal varies between the foldback starting voltage and the foldback ending voltage, respectively. In another form, a switched mode power converter uses such a switched mode power supply controller with an inductive element, switch, and feedback circuit.

A semiconductor component that includes a current limit circuit and a method for limiting current in the semiconductor component. An input/output pin is connected to the gate of a transistor and a control resistor is connected between the gate of the transistor and its source. One terminal of the control resistor is connected to the input/output pin and the other terminal is connected to another input/output pin. A current source is connected to the input/output pin. A reference voltage is generated between the two input/output pins and compared with a drain-source voltage that is between one of the two input/output pins and another input/output pin. A control voltage is set in accordance with the comparison. The control voltage then controls the voltage on another of the pins that is not common to the reference voltage and to the drain-source voltage.

Method for limiting current and circuit therefor

A numerically controlled oscillator (NCO) is arranged to accumulate control values for each transition of a system clock to provide an accumulation signal and an edge signal. A speed multiplier value (N) is selected to simulate a desired clock resolution of N times the system clock resolution. The multi-phase predictive clock circuit is arranged to provide clock phase output signals that each correspond to a predicted clock phase as if the system clock where running at N times faster than the actual system clock. The edge detector circuit is arranged to compare values of adjacent clock phases to identify a transition in one of the clock phases. The phase encoder circuit is arranged to provide a phase signal that indicates a transition in one clock phase. The edge signal and the phase signal can be used for careful phase alignment control at effectively higher resolution.

Numerically controlled oscillator

A buffered sample-and-hold circuit includes two sampling capacitors for each analog voltage to be sampled. The two sampling capacitors are initially charged simultaneously to the analog voltage to be sampled. One of such sampling capacitors is thereafter temporarily coupled to the input terminal of a unity gain amplifier to pre-charge such input terminal, and any associated parasitic capacitance, to a voltage very near the actual sampled analog voltage. Following such pre-charge operation, that sampling capacitor is de-coupled from the input terminal of the amplifier; the other sampling capacitor is then coupled to the input terminal of the amplifier for establishing the actual sampled voltage at the input terminal of the amplifier.

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Tempe, AZ, United States of America

Thomas Ciccone