International Business Machines Corporation

Thomas Charles Brennan

Kevin Charles Gower

Todd Alan Greenfield

Michael James Rohn

Daniel John Kolor

Robert F Lembach

Erik Victor Kusko

A method, system and computer program product are provided for implementing routing first for rapid prototyping and improved wiring of heterogeneous hierarchical integrated circuit chips. Placement for each of a plurality of random logic macros (RLMs) is identified. Predefined wiring shapes are created for each of the identified RLMs. Full chip wire routing is defined responsive to the created predefined wiring shapes for each of the identified RLMs.

Implementing routing first for rapid prototyping and improved wiring of heterogeneous hierarchical integrated circuits

A method of modifying an integrated circuit design. A noise threshold is determined. A threshold, noisy wire length for a particular integrated circuit design is selected. An integrated circuit design is examined for problem networks or wires and all branches that cumulatively equal or exceed the designated threshold noisy wire length. Once the problem networks are identified, the driver circuits driving the problem networks are temporarily replaced with driver circuits with lesser driving capacity. The integrated circuit design is then tested and any new timing failures are identified. Networks that include new timing failures are isolated with symmetric and/or asymmetric wire configurations. This method of modifying an integrated circuit design is non-intrusive to existing neighboring wires, and thus the timing in existing wires is preserved.

Method for isolating problem networks within an integrated circuit design

A method is shown which replaces single vias with redundant vias on candidate signals on a semiconductor integrated circuit chip. Where limited space prevents such replacement on more than one signal wire, the method assigns priority to the via through which more current must flow to charge or discharge capacitance. This prioritization reduces the magnitude of delay anomalies arising from vias containing process related resistance defects.

Method for adding redundant vias on VLSI chips

An automated method for designing a signal distribution network in an integrated circuit confines the circuits relating to a particular signal, such as a clock signal, to multiple areas equally distributed over the integrated circuit. Each of the multiple areas have tightly-coupled logic connected to a root driver circuit in which the root driver circuit is connected to the signal input. Within the areas of tightly-coupled logic, user-defined placement circuits or groups such as a programmable clock delay having gates, delays, and splitters are connected to the root driver circuit in accordance with wire capacitance targets and input pin load balancing among all the multiple areas. The input pin load balancing and the wire capacitance targets of the user-defined placement groups connected to the root driver circuit in one of the multiple areas matches the input pin load balancing and the wire capacitance targets of other groups connected to other root driver circuits in other multiple areas. Thus, skew is minimized during the automated placement of the design of the signal distribution network.

Automated placement of signal distribution to diminish skew among same capacitance targets in integrated circuits

A system and method for designing an integrated circuit device by selectively reducing power lines based on wiring demand of the device are provided. In one embodiment, a power demand value of a region of the device is determined and a wiring demand value of the region of the device is determined. Based on the wiring demand value and the power demand Value, power lines in the region are selectively reduced. These steps may be repeated for each region of the device and a new power line layout may be generated after stepping through each of the regions. The reduction of power lines may be repeated until an acceptable power line layout is produced. Based on this layout, detailed signal wiring can be performed. This technique can, for example, more efficiently allocate power lines and signal wires and increase the density of the integrated circuit chip.

Design of an integrated circuit by selectively reducing or maintaining power lines of the device

A method, apparatus, and article of manufacture for performing timing analysis on an integrated circuit, which run a high level chip timing tool with initial RC delays for all nets of the integrated circuit; determine a list of time-critical nets from a timing report and obtain a full RC coupling network for each time-critical net; run a detailed circuit simulator on the full RC coupling network for each time-critical net to obtain actual RC delays for each time-critical net; determine a delta time for each time-critical net, based on a difference between the initial RC delay and the corresponding actual RC delay for each time-critical net; and rerun the high level chip timing tool, including the delta time for each time-critical net to obtain a timing analysis of the integrated circuit which accounts for signal to signal noise.

Method and apparatus for performing integrated circuit timing including

A method and data processing system for graphically indicating a status of a circuit unit displayed within a circuit design on a display within a data processing system. The circuit unit displayed within the circuit design is selected, wherein the circuit unit is located at a location and has a first status. A movement of the selected circuit unit is detected. Whether the movement of the selected circuit unit changes the status of the selected circuit unit is determined. A status change of the selected circuit unit is automatically indicating by graphically indicating the status change in response to the change of status of the selected circuit unit, wherein the status of the selected circuit unit is dynamically indicated to a user in response to a movement of the selected circuit unit.

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Rochester, MN, United States of America

Thomas Charles Brennan