Mosel Vitelic Corporation

Other

Taiwan Imagingtek Corporation

Mosel Viltelic, Inc.

Thomas Chang

Liang-Choo Hsia

Min-Liang Chen

Chih-Hsien Wang

Hsiao-Chia Wu

Ing-Ruey Liaw

Kuo-Tung Sung

Liang-Chen Lin

Shih-Chi Lai

Chih-Ta Star Sung

Wen-Doe Su

Mao Song Tseng

Wen Hong Lee

Kun-Yu Sung

Jung-Cheng Kao

Jung Kao

Simon Chang

The present invention provides a new semiconductor Read-Only Memory, ROM, which stores more than one bit per cell. The potential of multiple threshold voltages combined with the potential multiple ratios of device channel width and length makes an ROM cell store multiple bits feasible. An N-type or a P-type MOS device of the standard CMOS process or a flat-cell mask ROM process are operable devices and processes in the design of this multi layer cell ROM. The ROM cell with smaller size is implemented to represent the LSB bits, while the larger size ROM cell is to represent the MSB bits.

Semiconductor ROM device and manufacturing method thereof

An EPROM cell and a method that includes a gate structure having a sidewall spacer. The sidewall spacer is made by way of an amorphous or polycrystalline silicon layer, which is converted into an insulating layer such as silicon dioxide. Deposition of the amorphous or polycrystalline silicon layer is more accurate and produces a more uniform layer than conventional dielectric layer deposition.

Flash memory process using polysilicon spacers

The present invention provides an improved method for forming metalization layers for inter-layer connections including the steps of first providing a substrate, then depositing a metal layer on the substrate, then depositing a dielectric layer overlying the metal layer, etching away an opening in the dielectric layer to expose at least partially the metal layer, and etching an opening in the metal layer by using the dielectric layer as a mask to at least partially expose the underlying substrate. The method may optionally includes the step of blanket depositing a thin oxide layer and then an inter-level dielectric layer on top of the device.

Method for forming metalization for inter-layer connections

An antireflection coating (116) for use in fabricating integrated circuits and electronic devices comprises a film of chromium oxide, CrO, or chromium suboxide, CrO.sub.x where x&lt;1. An antireflection layer reduces the standing waves and topographic notching in a photoresist layer (118) when applied over a highly reflective layer (114). Highly reflective layers may be metals, such as aluminum or gold, silicides, or semiconductors, such as silicon. These coatings are preferably made by reactive sputtering of a chromium target with a partial pressure of oxygen in the sputtering chamber. The antireflection layer works primarily by absorptive, rather than wave matching, principles. This antireflection layer exhibits good adhesion and may be integrated into the device. Integrating the layer into the device may reduce stress in the underlying layers and improve device yields and reliability.

Circuit structure with an anti-reflective layer

A method of forming a capacitor that has improved charge storage capacity in a high density memory device that has shallow trench isolation regions and a capacitor produced by the method are provided. The method includes the step of forming an oxide spacer that consists of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a contact hole is first etched by a plasma etching technique, the hole is again decoratively etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a corrugated side-wall of the contact hole is formed which affords the capacitor cell with an increased surface area leading to an improved charge storage capacity.

Stacked capacitor having improved charge storage capacity

The present invention discloses a double poly metal oxide/nitride/oxide semiconductor electrically erasable programmable read only memory (EEPROM) for use in semiconductor memories. The EEPROM structure includes a select gate, an oxide.backslash.nitride.backslash.oxide layer, and a control gate. The control gate is formed on the oxide.backslash.nitride.backslash.oxide layer. A lightly doped drain (LDD) structure is formed adjacent to the drain and underneath the control gate.

Method of making double-poly MONOS flash EEPROM cell

A method of fabricating single-side corrugated cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells. The corrugated capacitor shape is achieved by depositing the thermal chemical vapor deposition (CVD) oxide and the plasma-enhanced CVD (PECVD) oxide alternating layers. Then, the thermal CVD oxide and the PECVD oxide layers are lateral etched by hydrofluoric acid (HF). Because hydrofluoric acid (HF) etches the thermal CVD oxide at a slower rate than etches the PECVD oxide, a cavity (undercut) is formed in each PECVD oxide layer. Therefore, the single-side corrugated shape capacitor surface is created that increases the surface area of the capacitor considerably. The cylindrical capacitor storage node of the DRAM capacitor of this method has much greater surface area so as to increase the capacitance value of the DRAM capacitor, that can achieve high packing density of the integrated circuit devices.

Single-side corrugated cylindrical capacitor structure of high density

A method of forming a capacitor that has improved charge storage capability and a capacitor produced by such method are provided. The method utilizes an additional layer of oxide spacer consisting of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a contact hole is first etched by a plasma etching technique, the hole is again etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a corrugated side-wall of the contact hole is formed which affords the capacitor cell with a substantially increased surface area leading to an improved charge storage capability.

Method of forming stacked capacitor having corrugated side-wall structure

A method of fabricating double-side corrugated cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells. The corrugated capacitor shape is achieved by depositing the thermal chemical vapor deposition (CVD) oxide and the plasma-enhanced CVD (PECVD) oxide alternating layers. Then, the thermal CVD oxide and the PECVD oxide layers are vertically etched to form two trenches followed by laterally etched by hydrofluoric acid (HF). Because hydrofluoric acid (HF) etches the thermal CVD oxide at a slower rate than etches the PECVD oxide, a cavity is formed in each PECVD oxide layer along the trenches. Finally, polysilicon layer is deposited filling into the trenches. Therefore, the double-side corrugated shape capacitor surface is created that increases the surface area of the capacitor considerably. The cylindrical capacitor storage node of the DRAM capacitor of this method has much greater surface area so as to increase the capacitance value of the DRAM capacitor, that can achieve high packing density of the integrated circuit devices.

Double-side corrugated cylindrical capacitor structure of high density

A PMOS thin film transistor (TFT) with self-align offset region for SRAM application is described. A source and a drain regions are above the gate region. A channel region is formed offset from the gate. An offset region is formed in the channel region having a length of 0.3 to 0.4 .mu.m. The key point of the present invention is the novel offset design of PMOS-TFT as load elements in an SRAM cell. Unlike the conventional offset design which is outside the gate, the offset region of the present invention is a disconnection region inside the gate which can be easily formed by so called self-align technique. Since the gate has a disconnected portion in the offset region, the trench-like profile of the offset region makes the load resistance in the offset region much higher to effectively reduce the leakage current.

TFT with self-align offset gate

A novel electrically erasable programmable read only memory (EEPROM) cell for use in semiconductor memories includes a polyspacer floating gate. The EEPROM structure also includes a select gate covering a part of the channel of the EEPROM cell, with a polysilicon spacer adjacent to the select gate. The polysilicon spacer implements a floating gate that holds charge to program the EEPROM cell. In one embodiment, a isolation layer separates the select gate and the floating gate. The isolation layer and the floating gate extends over the remaining part of the channel. A second isolation layer is formed over select gate and the floating gate. A control gate is formed on the isolation layer. Between the drain and the control gate is the second isolation layer. A lightly doped drain (LDD) structure is formed at the drain adjacent.

Method of making EEPROM cell device with polyspacer floating gate

A method of forming a cell contact that has improved structural strength and break-down resistance and a cell contact produced by such method are provided. The method utilizes an oxide spacer consisting of a plurality of oxide layers deposited by two alternating methods of thermal CVD and plasma CVD. After a straight contact opening is first etched by a plasma etching technique, the hole is again etched by an etchant such as hydrogen fluoride which has a high selectivity toward oxide layers formed by the plasma CVD method and a low selectivity toward oxide layers formed by the thermal CVD method. As a result, a contact opening having a corrugated side-wall is formed and into which a polysilicon is deposited to substantially fill the hole. A cell contact having a corrugated side-wall configuration is thus formed which presents improved structural rigidity and break-down resistance. A layer of rugged polysilicon layer may optionally be deposited before the deposition of the polysilicon into the contact opening to further increase the surface area of the cell contact.

Method of making corrugated cell contact

The present invention relates to a method of fabricating a SRAM cell that has a low stand-by current. A second polysilicon layer which is used as polysilicon resistor is exactly over a first polysilicon layer. The double polysilicon layer is utilized to reduced a stand-by current. A electric field is generated between the two layers caused by applying different voltage to the two polysilicon layer respectively, and the carriers in the second polysilicon layer will be repeled to form a depletion region, which will increase the resistance of the second polysilicon layer. Therefore, the stand-by current (Isb) will be reduced.

Method of manufacturing a SRAM cell having a low stand-by current

The present invention relates to an automatic temperature controlling system for semiconductor process, when one of the chillers in the temperature controlling system is out of order, then another chiller will automatically take over the function of the broken one by using the second temperature controlling path. The automatic temperature controlling system includes: at least two chambers used for performing a process having first temperature controlling paths for providing coolant circulations while the system is in normal condition, and having a second temperature controlling path for providing at least one coolant circulation while the system is in abnormal condition; at least two chillers are respectively connected to the chambers for controlling the temperature of the chambers; a plurality of first normal-on valves are used to control the condition of the first temperature controlling paths; a plurality of second normal-on valves are used to control the condition of the first temperature controlling paths; and a plurality of pairs of normal-off valves are used to control the condition of the second temperature controlling paths.

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Taichung, Taiwan

Thomas Chang