Other

Andapt, Inc.

Apple Inc.

Purdue Research Foundation

Industrial Technology Research Institute

The Celotex Corporation

International Technology Research Institute

Thomas Chan

Patrick J Crotty

John Birkner

Kapil Shankar

Chi Chen Hsien

Andrew K Chan

Kok S Chen

Qinggang Zhou

Clyde H Nagakura

Ching-jer Chang

Fen-Lan Lin

Chen-Tao Lee

David Waters

Curtis L Ashendel

Robert L Geahlen

Jih-Dar Tsai

Andrew Brandon Chan

Minjong Kim

Po Weng Chiu

Ching Te Chang

Ching Tien Chang

Harry J Raftopoulos

Andrew Lyon Chan

Apparatuses of reusable diapers with feces sensing and methods for manufacturing the same are provided. In one embodiment, a diaper includes an interior layer includes an excretion area, where the excretion area includes one or more openings configured to drain excretions of a user away from the interior layer; a middle layer configured to house an excretion collection unit, where the excretion collection unit is configured to store the excretions from the interior layer, and the middle layer further includes a feces sensing unit configured to detect feces discharged from the user; a feces monitoring module electrically coupled to the feces sensing unit, where the feces monitoring module is configured to monitor the feces sensing unit and communicate status of the feces sensing unit to one or more caregivers; an exterior layer configured to conceal and prevent leakage from the middle layer of the diaper; and a support frame configured to hold the interior layer, the middle layer and the exterior layer of the diaper together.

Reusable diaper with feces sensing

Apparatuses of reusable diapers and methods for manufacturing the same are provided. In one embodiment, a diaper includes an interior layer includes an excretion area, where the excretion area includes one or more openings configured to drain excretions of a user away from the interior layer, a middle layer configured to house an excretion collection unit, where the excretion collection unit is configured to store the excretions from the interior layer, an exterior layer configured to conceal and prevent leakage from the middle layer of the diaper, and a support frame configured to hold the interior layer, the middle layer and the exterior layer of the diaper together.

Reusable diaper

Apparatuses of reusable incontinence underwear and methods for manufacturing the same are provided. In one embodiment, an incontinence underwear includes an interior layer includes an excretion area, where the excretion area includes one or more openings configured to drain excretions of a user away from the interior layer; a middle layer configured to house an excretion collection unit, where the excretion collection unit is configured to store the urine from the interior layer to a urine collection bag external to the incontinence underwear; an exterior layer configured to conceal and prevent leakage from the middle layer of the incontinence underwear; and a support frame configured to hold the interior layer, the middle layer and the exterior layer of the incontinence underwear together.

Reusable incontinence underwear

Apparatuses of reusable menstrual pad and methods for manufacturing the same are provided. In one embodiment, a menstrual pad includes an interior layer includes an excretion area, where the excretion area includes an opening configured to drain menstrual fluid of a user away from the interior layer; a middle layer configured to house a menstrual fluid collection unit, where the menstrual fluid collection unit is configured to sanitize the menstrual fluid drained from the interior layer and to store the sanitized menstrual fluid to one or more menstrual napkins in the middle layer; an exterior layer configured to conceal and prevent leakage from the middle layer of the menstrual pad; and a support frame configured to hold the interior layer, the middle layer and the exterior layer of the menstrual pad together.

Reusable menstrual pad

A power management integrated circuit (PMIC) includes: a plurality of high voltage power field effect transistors (FETs); and a programmable fabric configured to programmably connect one or more of the plurality of high voltage power FETs to provide one or more high power voltage outputs. The plurality of high voltage power FETs and the programmable fabric are integrated in a single chip.

Power management integrated circuit integrating field effect transistors and programmable fabric

An integrated analog and digital adaptive platform includes: a plurality of adaptive analog blocks, each of the plurality of adaptive analog blocks being integrated with a respective digital wrapper; and a programmable digital fabric configured to programmably connect one or more of the plurality of adaptive analog blocks by connecting a plurality of digital wrappers integrated with the one or more of the plurality of adaptive analog blocks. The plurality of adaptive analog blocks that are programmably connected using the programmable digital fabric provide one or more programmable analog functions.

Adaptive analog blocks with digital wrappers integrated onto programmable fabric

A programmable logic device (PLD) includes a programmable fabric, a plurality of input/output (I/O) blocks, and a plurality of high voltage power field effect transistors (FETs). The PLD can be programmed to connect one or more of the plurality of I/O blocks, one or more of the plurality of high voltage power transistors via the programmable fabric. Each of the plurality of high voltage power transistors includes a drain pad and a source pad that are exposed via external pins of the PLD.

Programmable logic device with integrated high voltage power FET

A high voltage power block includes a high voltage power transistor; and a switch driver configured to drive a gate of the high voltage power transistor. The high voltage power block is integrated in a programmable logic device (PLD) including a programmable fabric, a signal wrapper configured to provide signals between the high voltage power transistor and the programmable fabric, and a plurality of internal components. The plurality of internal components integrated in the PLD are programmably connected and characteristics of the high voltage power transistor are programmably adjusted using the programmable fabric and the signal wrapper.

Scalable integrated MOSFET (SIM)

An electronic music display and methods of using the same are disclosed. In one embodiment, the electronic music display comprises a display configured to display one or more pages of a music file, a first indicator imposed on a page of the music file to guide a user to issue a user command to display a next page, a receiver configured to receive the user command to display the next page wirelessly from a remote controller, and a controller configured to display the next page in response to the user command received is within a predetermined duration.

Apparatus and method of supporting communication and performance among a group of musicians

An electronic music display and methods of using the same are disclosed. In one embodiment, the electronic music display includes a user interface configured to receive one or more music files, a memory device configured to store the one or more music files, a controller configured to program the electronic music display in accordance with user specified requirements with respect to order of the one or more music files to be displayed and with respect to tempos that corresponding different sections of the one or more music files to be performed, and a display configured to display a sequence of pages of the one or more music files as programmed.

Electronic music display

A display processor integrated circuit (for example, for a television or for a digital camera) includes a display processor portion and an on-chip programmable logic portion. The on-chip programmable logic portion can be configured or programmed to implement custom video and/or image enhancement functions. Accordingly, an individual television or camera manufacturer can have his/her own custom enhancement function incorporated into the display processor integrated circuit by having the programmable logic portion configured or programmed appropriately. In one embodiment, the programming of the programmable logic portion involves changing just one mask, thereby reducing the cost, complexity and time associated with implementing the custom video/image enhancement function.

Display processor integrated circuit with on-chip programmable logic for implementing custom enhancement functions

A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

Segment buffer loading in a deinterlacer

A method is disclosed whereby an inexpensive integrated circuit is provided for use in high volume electronic consumer devices of different makes, wherein each different make must perform a different special function. A common function required in all the different makes is realized in a substantially non-customizable portion. A dense mask-programmable portion is provided for realizing a special function. Interface circuitry is provided that enables an external FPGA to perform the special function at system operating speeds during system development. After system development, the circuitry implemented in the external FPGA is technology-mapped to the mask-programmable portion. A single mask is fashioned such that versions of the integrated circuit are produced with their mask-programmable portions customized to perform the special function. I/O terminals that were used to couple to the external FPGA during system development are usable during normal operation to provide system board access to circuitry within the mask-programmable portion.

Growing community of inventors

Saratoga, CA, United States of America

Thomas Chan