Cirrus Logic Inc.

Telefonaktiebolaget Lm Ericsson (publ)

Thomas C Yip

Michael Feng

Edward Ho

Ranjit Joseph Rozario

Edmund C Chen

Hemanth G Kanekal

Patrick Wang

Sun Den Chen

Stephen Chow

Arvind K Kansal

Ramanathan Lakshmikanthan

Brian Alleyne

Srivathsa Dhruvanarayan

Sun-den Chen

Jeffrey Hu

Srivi Dhruvanarayan

A method is implemented by a network element to provide scalable hierarchical traffic management (HTM) over a plurality of network layers for a network and eliminate priority leaking caused by quick loopback batch scheduling that analyzes a subset of network layers to shorten processing time and resource requirements when the scalable HTM selects data packets to be forwarded. The method and system function as a low pass filter over the selected data packets to prevent low priority data packets being forwarded where higher priority data packets are available to be forwarded.

Low pass filter for hierarchical pipelined distributed scheduling traffic manager

Embodiments of the invention include a method for avoiding memory bandwidth utilization during packet processing. The packet processing core receives a plurality of packets. The packet processing core identifies the packet's quality of service (QoS) descriptor. The packet processing core determines that at least one packet should be moved to an off-chip packet stored prior to the packet being transmitted to the egress port. The packet processing core bases that determination, at least in part, on the packet's QoS descriptor. The packet processing core moves the determined packets to the off-chip packet store. The packet processing core determines that at least one packet should not be moved to the off-chip packet store prior to the packet being transmitted to the egress port. This determination is also made, at least in part, based on the packet's QoS descriptor.

On-chip packet cut-through

A hierarchical pipelined distributed scheduling traffic manager includes multiple hierarchical levels to perform hierarchical winner selection and propagation in a pipeline including selecting and propagating winner queues of a lower level to subsequent levels to determine one final winning queue. The winner selection and propagation is performed in parallel between the levels to reduce the time required in selecting the final winning queue. In some embodiments, the hierarchical traffic manager is separated into multiple separate sliced hierarchical traffic managers to distributively process the traffic.

Hierarchical pipelined distributed scheduling traffic manager

A method and apparatus for integrating a row address strobe signal monitoring circuit in a graphics controller is described. The present invention includes an improved graphics controller comprising a bi-directional input/output pad and a row address strobe signal snooping circuit to monitor the row address strobe signal to detect the pre-charge status of the signal prior to a memory access by the graphics controller. The input/output pad of the present invention enables the graphics controller to simultaneously receive and drive a row address strobe signal upon being granted permission to access memory. The row address snooping method of the present invention enables the graphics controller to pre-charge the row address strobe signal while the controller is in an inactive memory access state. Pre-charging the row address signal allows the graphics controller to immediately drive a pre-charged address strobe signal to memory upon receiving permission to access memory; thereby reducing the number of clocks it takes the graphics controller to access memory.

Method and apparatus for monitoring a row address strobe signal in a

A graphics controller that uses two MREQ priority levels (low and high) to retrieve display data from a frame buffer into a CRT FIFO. The graphics controller sends the high priority MREQ signal to a host controller if the data level in the CRT FIFO is below a low level water mark. The graphics controller sends the low priority MREQ signal if the data level in the CRT FIFO is between a high level water mark and a low level water mark, and if a system memory bus is idle. The host controller grants access of the system memory bus to the graphics controller with a higher priority (i.e. above that of other devices such as CPU and I/O devices) in response to the high priority MREQ signal, and with a lower priority in response to the low priority MREQ signal. Upon being granted access to the system memory bus, the graphics controller retrieves display data from the frame buffer. By employing the low priority MREQ signal, the system memory bus is more efficiently utilized and the frequency of high priority MREQ signals is minimized which leads to an overall increase in the throughput performance of the information processing system.

Method and apparatus for reading ahead display data into a display FIFO

An apparatus and method for acquiring address and command information related to a synchronous bus transaction with at most zero hold-time over substantially the duration of the bus transaction. Due to state changes, bus transaction address and command information may become invalid over the duration of the bus transaction. A transparent latch circuit is used to make the information available as soon as the information is received and to acquire valid information related to the bus transaction before a rising clock edge of the next clock cycle following a bus transaction request. A synchronous flip-flop circuit is utilized simultaneously to capture alternate valid information related to a bus transaction having at most zero hold-time. The acquired valid information and the alternately acquired valid information ensure that stable and valid bus transaction information are available over substantially the duration of the transaction. Moreover, by decoding the information as soon as they are received (i.e., before the transparent latch circuit closes), a fast bus transaction acknowledgement signal can be generated.

Method and apparatus for acquiring bus transaction address and command

An apparatus and method for acquiring data information provided by a synchronous bus transaction with at most zero hold-time. A transparent latch circuit is used to capture bus transaction information before a rising clock edge of the next clock cycle following a bus transaction request and a data phase starting signal thereby meeting the zero-hold requirement. At the same time, bus transaction information is decoded to determine whether the current phase is a data phase, data information is present in the current bus transaction, memory addresses presented are within an allowable range, and bus transaction command is of the type recognized. If all the above conditions are met, the information captured by the transparent latch circuit is registered by a synchronous flip-flop circuit as valid data information.

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Los Gatos, CA, United States of America

Thomas C Yip