Ramtron International Corporation

Nippon Steel Semiconductor Corporation

Thomas C Taylor

Richard Allen Bailey

E Henry Stevens

Douglas Blaine Butler

A method of fabricating a metal-ferroelectric-metal ('MFM') capacitor includes the steps of depositing a silicon dioxide layer on a silicon or other substrate, a lower platinum or other noble metal electrode, a PZT or other ferroelectric material dielectric layer, and an upper platinum or other noble metal electrode. The upper electrode and ferroelectric dielectric layer are patterned and etched according to a first pattern corresponding to the final dimensions of the ferroelectric dielectric layer. The upper electrode and lower electrode are subsequently patterned and etched according to a second pattern corresponding to the final dimensions of one or more upper electrodes and the final extent of the lower electrode. The second etching step leaves a benign vestigial upper electrode feature. An oxide layer is finally deposited over the entire surface of the MFM capacitor structure, which is etched and metalized over desired upper and lower electrode contacts.

Fabrication of metal-ferroelectric-metal capacitors with a two step

In fabricating a source/drain electrode of an integrated circuit transistor and a contact window for it: (1) establishing a structure with a window over the source/drain region next to a gate electrode and isolation structure; (2) establishing a dielectric layer covering the isolation structure, the window, and gate electrode; (3) implanting a moderate concentration of impurities into the source/drain region through said dielectric layer so that the moderate concentration region extends partially under the gate electrode; (4) removing the horizontal portions of the dielectric layer with an anisotropic etch thereby leaving the dielectric on vertical side walls; (5) establishing a region of titanium silicide over the moderately dosed source/drain region and establishing a titanium nitride layer over the isolation structure, windows, and gate electrode; (6) establishing a layer of silicon nitride over the titanium nitride layer; (7) implanting the substrate with a relatively heavier dose of ions through the silicon nitride, titanium nitride, and titanium silicide layers to create a heavier concentration source/drain region intersecting said moderate concentration region, where the heavy concentration region does not underlie the gate electrode; (8) patterning the silicon nitride layer; (9) using the patterned silicon nitride layer as a mask to pattern the titanium nitride layer; (10) adding thick interlevel dielectric over the patterned nitride layers; (11) opening windows over the electrodes; and (12) adding contact material in said windows.

Process for fabricating transistors using composite nitride structure

In fabricating a contact window to source/drain electrode next to a gate electrode of an integrated circuit: (1) establishing a structure with a window over the source/drain region next to the gate electrode; (2) establishing a region of titanium silicide over the source/drain electrode and establishing a titanium nitride layer over the window and gate electrode; (3) establishing a layer of silicon nitride over the titanium nitride layer; (4) patterning the silicon nitride layer; (5) using the patterned silicon nitride layer as a mask to pattern the titanium nitride layer; (6) adding another silicon nitride layer to seal the gate electrode where it is not protected by titanium nitride; (7) opening a window over the electrode by an anisotropic etch; (8) widening the window with an isotropic etch, using the silicon nitride and titanium nitride as a protective barrier; and (9) adding contact material in said windows.

Growing community of inventors

Colorado Springs, CO, United States of America

Thomas C Taylor