Topside Research, LLC

Avago Technologies General IP (singapore) Pte. Ltd.

Thomas C Reiner

Chris Haywood

Heath Stewart

Michael J De La Garrigue

Ken Wong

Adam Rappoport

Bao K Vuong

Nadim Shaikli

Phil Terry

Kirk Jong

Neely Walls

Mike De La Garrigue

There is disclosed apparatus and methods of multicasting in a shared address space. A shared memory address space may include two or more multicast portions. Each multicast portion may be associated with a respective end point and with at least one other multicast portion. Data units may be transmitted to at least some of the end points via memory-mapped I/O into the shared memory address space. When a destination address of a data unit is in a first multicast portion associated with a first end point, the data unit may be transmitted to the first end point, revised to specify a destination address in a second multicast portion associated with the first multicast portion, and transmitted to a second end point associated with the second multicast portion.

Multicasting computer bus switch

A network processor having bypass capability in which some data units are diverted from being processed by the processor core of the network processor. In one embodiment, a network processor may include a receiver to receive data units, configuration information used to evaluate whether the data units require processing, a processor core to process data units that require processing, a bypass store to hold those data units which do not require processing by the processor core, and a transmitter to transmit the data units. In one embodiment, a method may include receiving a plurality of data units, receiving configuration information, evaluating whether each of the data units requires processing based on the configuration information, bypassing processing those of the data units that do not require processing based on the evaluating, processing those of the data units that require processing based on the evaluating, and transmitting the data units.

Network processor having bypass capability

There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

Optimized switching method

There is disclosed apparatus and methods of multicasting in a shared address space. There may be defined a number of portions of the address space. There may be groups of the portions, and data units addressed to one portion within the group may be re-addressed to the other portions.

Multicasting in a shared address space

Switch for bus optimization

Growing community of inventors

Agoura Hills, CA, United States of America

Thomas C Reiner