Ip-first, LLC

Centaur Technology, Inc.

Via Technologies, Inc.

International Business Machines Corporation

Thomas C McDonald

G Glenn Henry

John Duncan

Brent Bean

Terry J Parks

Gerard M Col

Timothy Jon Sulzbach

A quick predictor override system and method for a microprocessor that enables a correction to a quick predictor, branch prediction by a branch target address cache (BTAC), and rapid update to the quick predictor. For example, the microprocessor includes a quick predictor that provides branch prediction based on a local pattern history, and a large predictor in the form of the BTAC, which provides for branch prediction using a global pattern history. Branch prediction by the BTAC is the prevailing prediction if different, for a fetched cache address, than the branch prediction by the smaller, quick predictor. Accordingly, the target and direction for conditional branches provided by the BTAC for fetching the next cache instruction are used in favor of the target and direction previously provided by the quick predictor, and the quick predictor is quickly updated with the target and direction from the BTAC during a BTAC stage.

Quick predictor override and update by a BTAC

In one embodiment, a method implemented in a microprocessor, including receiving a fetched branch instruction; performing a privilege level test on a fetched branch instruction using a privilege level indicated by a first tag corresponding to a privilege level in a branch prediction table comprising plural entries, each of the plural entries comprising a tag corresponding to a privilege level; and providing a prediction branch miss for the fetched branch instruction based on a failure of the privilege level test.

Spectre fixes with predictor mode tag

In one embodiment, a branch prediction control system is configured to move a mispredicted conditional branch from a smaller cache side that uses the lower complexity conditional branch predictor to one of the two large cache sides that uses the higher complexity conditional branch predictors. The move (write) is achieved according to a configurable probability or chance to escape misprediction recurrence and results in a reduced amount of mispredictions for the given branch instruction.

Small branch predictor escape

In one embodiment, a microprocessor, comprising: first logic configured to dynamically adjust a maximum prefetch count based on a total count of predicted taken branches over a predetermined quantity of cache lines; and second logic configured to prefetch instructions based on the adjusted maximum prefetch count.

Branch density detection for prefetcher

In one embodiment, a microprocessor, comprising: a branch prediction table comprising plural entries, wherein at least a portion of the plural entries corresponds to an indirect branch type; and an indirect valid table; wherein based on an indirect branch instruction fetch, an entry corresponding to an indirect branch instruction in the branch prediction table is configured as invalid based on clearing a corresponding entry in the indirect valid table.

Spectre fixes with indirect valid table

In one embodiment, a branch processing method comprising receiving information from at least two branch execution units; writing two updates per clock cycle to respective first and second write queues based on the information; and writing from the first write queue up to two updates per clock cycle into plural tables of a first predictor and a single update for the single clock cycle when there is an expected write collision, the first predictor comprising a single write or read/write port.

Dual branch execute and table update with single port

In one embodiment, a branch processing method, comprising: assigning plural branch instructions for a given clock cycle to primary branch information and secondary branch information; routing the primary branch information along a first path having adder logic and the secondary branch information along a second path having no adder logic; and writing the primary branch information including a displacement branch target address to a branch order table (BOT) and the secondary branch information without a target address to the BOT.

Dual branch format

In one embodiment, a microprocessor, comprising: an instruction cache configured to receive an instruction fetch comprising a first byte portion and a second byte portion; a side cache tag array configured to signal further processing of the second byte portion in addition to the first byte portion based on a hit of the side cache tag array; and a side cache data array configured to store instruction data for the second byte portion.

Side cache array for greater fetch bandwidth

In one embodiment, a microprocessor, comprising: prediction logic comprising a branch predictor comprising a group of multi-set associative tables, each of the tables corresponding to branch pattern histories of different lengths; and control logic configured to provide an adjustable write policy for the prediction logic.

Adjustable write policies controlled by feature control registers

In one embodiment, a microprocessor, comprising: first logic configured to detect that a fetched cache address matches at least one of two previous cache addresses; and second logic configured to adjust a branch pattern used for conditional branch prediction based on the match and combine the cache address with the adjusted branch pattern to form a conditional branch predictor address.

Speculative branch pattern update

In a microprocessor that has an instruction set architecture in which the instructions may include a variable number of prefix bytes, an apparatus for efficiently extracting instructions from a stream of undifferentiated instruction bytes. Decode logic determines which byte is an opcode byte for each instruction of a plurality of instructions within the stream of undifferentiated instruction bytes. The opcode byte is the first non-prefix byte of the instruction. The decode logic accumulates prefix information onto the opcode byte of the instruction for each instruction of the plurality of instructions. A queue holds the stream of undifferentiated instruction bytes and the accumulated prefix information. Extraction logic extracts the plurality of instructions from the queue in one clock cycle independent of the number of prefix bytes included in each of the plurality of instructions.

Prefix accumulation for efficient processing of instructions with multiple prefix bytes

A microprocessor includes a branch target address cache (BTAC), each entry thereof configured to store branch prediction information for at most N branch instructions. An execution unit executes a branch instruction previously fetched in a fetch quantum. Update logic determines whether the BTAC is already storing information for N branch instructions within the fetch quantum (N is at least two), updates the BTAC for the branch instruction if the BTAC is not already storing information for N branch instructions, determines whether a type of the branch instruction has a higher replacement priority than a type of the N branch instructions if the BTAC is already storing information for N branch instructions, and updates the BTAC for the branch instruction if the type of the branch instruction has a higher replacement priority than the type of the N branch instructions already stored in the BTAC.

Efficient branch target address cache entry replacement

An apparatus in a microprocessor that has an instruction set architecture in which instructions may include a length-modifying prefix used to select an address/operand size other than a default address/operand size, wherein the apparatus marks the start byte and the end byte of each instruction in a stream of instruction bytes. Decode logic decodes each instruction byte of a predetermined number of instruction bytes to determine whether the instruction byte specifies a length-modifying prefix and generates a start mark and an end mark for each of the instruction bytes based on an address/operand size. Operand/address size logic provides the default operand/address size to the decode logic to use to generate the start and end marks during a first clock cycle during which the decode logic decodes the predetermined number of instruction bytes. If during the first clock cycle and any of N subsequent clock cycles the decode logic indicates that one of the predetermined number of instruction bytes specifies a length-modifying prefix, the operand/address size logic provides to the decode logic on the next clock cycle the address/operand size specified by the length-modifying prefix to use to generate the start and end marks.

Apparatus and method for marking start and end bytes of instructions in a stream of instruction bytes in a microprocessor having an instruction set architecture in which instructions may include a length-modifying prefix

An apparatus efficiently determines the length of an instruction within a stream of instruction bytes processed by a microprocessor having a variable instruction length instruction set architecture. The apparatus includes combinatorial logic associated with each instruction byte of the stream, each configured to receive the associated instruction byte and the next instruction byte of the stream and to generate in response thereto a first length, a second length, and a select control. A multiplexor associated with each of the combinatorial logic selects and outputs one of the following inputs based on the select control received from the combinatorial logic: a zero input and the second length received from the combinatorial logic associated with each of the next three instruction bytes of the stream. An adder associated with each of the combinatorial logic and multiplexor adds the first length and the output of the multiplexor to generate the length of the instruction.

Apparatus for efficiently determining instruction length instruction within a stream of x86 instruction bytes

An apparatus for extracting instructions from a stream of undifferentiated instruction bytes in a microprocessor having an instruction set architecture in which the instructions are variable length. Decode logic decodes the instruction bytes of the stream to generate for each a corresponding opcode byte indictor and end byte indicator and receives a corresponding taken indicator for each of the instruction bytes. The taken indicator is true if a branch predictor predicted the instruction byte is the opcode byte of a taken branch instruction. The decode logic generates a corresponding bad prediction indicator for each of the instruction bytes. The bad prediction indicator is true if the corresponding taken indicator is true and the corresponding opcode byte indicator is false. The decode logic sets to true the bad prediction indicator for each remaining byte of an instruction whose opcode byte has a true bad prediction indicator. Control logic extracts instructions from the stream and sends the extracted instructions for further processing by the microprocessor. The control logic foregoes sending an instruction having both a true end byte indicator and a true bad prediction indicator.

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Austin, TX, United States of America

Thomas C McDonald