Texas Instruments Corporation

Other

Thomas C Holloway

Roger A Haken

Howard L Tigelaar

Che-Chia Wei

Thomas E Tang

Robert Groover, Iii

David A Bell

Al F Tasch, Jr

Douglas Ticknor Grider

Richard A Chapman

Pallab K Chatterjee

James L Paterson

Sunil V Hattangady

Horng-Sen Fu

William R Hunter

A transistor is formed on the substrate (,) with a graded doping profile for the gate electrode (,). This graded profile is performed for an N-channel transistor by depositing the gate electrode with two separate layers of material. The first layer is a thin layer of N-doped poly, whereas the second layer is a layer of P-doped poly (,). A layer of cap oxide (,) is disposed over the gate electrode (,) to prevent further implantation of impurities during the source/drain implant operation.

Variable threshold voltage gate electrode for higher performance mosfets

A gate electrode of a MOS transistor wherein gate oxide 12 is placed over substrate 10. Boron-doped polysilicon gate electrode 14 is placed over gate oxide 12. Optionally, drain extender implants may be added to substrate 10. Low-temperature-deposited nitride layer 18 is placed over gate electrode 14 and gate oxide 12. The structure then undergoes a sidewall spacer etch to form sidewall spacers 20.

Method to reduce boron diffusion through gate oxide using sidewall

A memory circuit (10) is provided. The memory circuit comprises a flip-flop (12) and first and second pass gate transistors (14) and (16). The flip-flop (12) also comprises pull down transistors (18) and (20). The gate of each pull down transistor (18) and (20) is doped at a level that is greater than the doping level for each gate of pass gate transistors (14) and (16).

Memory circuit and method of construction

A method of providing a MOSFET having improved gate oxide diffusion barrier properties, which comprises providing a partially fabricated MOSFET having an exposed gate oxide surface. During MOSFET fabrication, the surface of the exposed gate oxide is converted to an oxynitride by applying one or both of ions or free radicals of nitrogen to the exposed gate oxide surface. Fabrication of the MOSFET is then completed in standard manner.

Method of improving diffusion barrier properties of gate oxides by

A method of fabricating a semiconductor device and the device. There is provided a substrate (21) of semiconductor material. A gate electrode (25) is formed over the substrate (21) having a sidewall (27) and electrically isolated from the substrate. Source/drain regions (29, 31) are formed in the substrate defining a channel in the substrate extending beneath the gate electrode. One of a pocket region or a halo region (33) extending substantially entirely under the gate electrode and sidewall is then formed. The pocket region or halo region is formed by providing a compensating species which is implanted at the time of the source/drain implant in order to compensate the doping increase under the source/drain caused by the pocket or halo implant. Since the implant dose and range of this compensating implant is comparable to the pocket or halo implant, no penetration of the gate electrode should occur. Also, since the compensating implant is performed after the sidewall spacer is formed, the pocket or halo is not compensated in the region wherein it is required for reduction of MOS transistor short channel effects.

Method to reduce diode capacitance of short-channel MOSFETS

The invention comprises a method of forming a semiconductor device is provided where a first gate insulator layer 26 is formed on an outer surface of semiconductor substrate 24. A mask body 28 is formed to cover portions of the insulator layer 26. The exposed portions of the layer 26 are subjected to a nitridation process to form a nitride layer 30. A second oxidation process forms a thick gate oxide layer 32. The nitride layer 30 inhibits the growth of oxide resulting in a single integrated device having gate insulator layers having two different thicknesses such that high voltage and low voltage transistors can be formed on the same integrated circuit.

Semiconductor device having dual gate and method of formation

A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. Normally this conductive layer is stripped to avoid shorting out devices. However, the present invention patterns this conductive layer, thereby providing a local interconnect with the sheet resistance of the order of one ohm per square. Moreover, this local interconnect level permits contacts to be misaligned with the moat boundary, since the titanium nitride local interconnect layer can be overlapped from the moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide. This local interconnect level fulfills all of the functions which a buried contact layer could fulfill, and fulfills other functions as well.

VLSI interconnect method and structure

Disclosed is an integrated circuit process which includes forming two types of active devices: a first set of IGFETs has silicide gates, and the second set has TiN gates. The same TiN thin film layer also provides local interconnect. Optionally the TiN-gate devices may be used for high-voltage devices and the silicide-gate devices used for logic devices. The TiN gates in the second set of transistors and the TiN interconnect are formed by providing a thin film insulator pattern, depositing a titanium layer overall, heating the titanium in a nitrogen bearing atmosphere, and subsequently etching the titanium nitride obtained.

Integrated circuit process with TiN-gate transistor

A new DRAM structure, wherein the top plate of the storage capacitor is provided by a TiN thin film layer 410', and the bottom plate is provided by a polysilicon layer 402' which also provides the gates 402 of the pass transistors.

Single-polysilicon dram device and process

Polysilicon gate insulated gate field effect transistors with threshold adjustment implants made after the gate oxide (156) and a split of the polysilicon gate (158) have been formed provides a shallow, tight dopant profile.

Threshold adjustment method for an IGFET

VLSI local interconnect structure

A new integrated circuit structure which includes two types of active devices: a first set of IGFETs has silicide gates, and the second set has TiN gates. The same TiN thin film layer also provides local interconnect. Optionally the TiN-gate devices may be used for high-voltage devices and the silicide-gate devices used for logic devices.

Integrated circuit device and process with tin-gate transistor

An integrated circuit including doubled capacitors (metal/dielectric/TiN/dielectric/polysilicon). This structure is preferably made using a patterned interlevel oxide/nitride layer to split a polycide layer, i.e. at some locations the polycide layer has low sheet resistance and at other locations the polycide layer is vertically split to provide two layers (TiN and unsilicided polysilicon), which are separated by the interlevel oxide/nitride. A double contact etch is used before the first metal interconnect layer is deposited, so that the metal makes ohmic contact to underlying silicide or silicon or TiN in some locations, and in others provides insulated metal top plates over TiN/polysilicon capacitance to provide doubled capacitors.

Device and process with doubled capacitors

A new integrated circuit structure, wherein a TiN thin film layer 129 and another patterned thin film layer 124 preferably comprising polysilicon are separated (in some locations) by a thin dielectric 132 to define capacitors. At various other locations, the TiN layers 129 also makes contact to the polysilicon layer 124 (which will be silicide-clad at these locations), makes contact to n+ substrate regions 134 and p+ substrate regions 136, and also to provide a contact pad for a third patterned thin film conductor layer which overlies the other two. One important class of embodiments provides a floating-memory cell. wherein the floating gate 120 is made of polysilicon, but the control gate 142 consists predominantly of titanium nitride. A novel process for forming the titanium nitride control gate 142 and simultaneously forming titanium nitride local interconnect lines 149 is also disclosed.

Integrated circuit device and process with tin capacitors

Disclosed is a process for making VLSI integrated circuits and a local interconnect system, wherein first poly, second poly and moat are all interconnected in any desired pattern by a TiN local interconnect. No masks are required beyond those which would be required for the two poly levels and local interconnect capability anyway.

Growing community of inventors

Dallas, TX, United States of America

Thomas C Holloway