Motorola Corporation

Thomas C Daly

Rodney J Means

Edward C Hepworth

Stanley E Groves

Gene A Schriber

Brian M Spinks

Richard M Baker

A programmable timer module (PTM) is provided as a component of a microprocessor system in order to generate and measure varying time intervals under program control. The programmable timer module includes, in one embodiment, three independent 16-bit timers. Each timer includes a 16-bit counter and a 16-bit latch. The programmable timer module also includes an 8-bit status register and an 8-bit control register each of which may be coupled to an 8-bit bidirectional data bus of a microprocessor system. Selection circuitry is provided which permits the microprocessor to select either the control register or the status register. Information can be written into the control register; the operation is effected by means of read/write circuitry and a read/write input. Any one of the three timers can also be selected by means of the selection circuitry, and a 16-bit number can be written into the selected 16-bit latch. Reset circuitry resets the counter whenever the 16-bit latch is written into, and the counter counts until it reaches the number written into the 16-bit latch, whereupon the interrupt circuitry generates an interrupt signal and sets an appropriate interrupt bit in the status register, and also resets that counter. The counter continues counting at the appropriate clock rate after the interrupt so that time since the interrupt may be determined by the microprocessor. The outputs of the three counters can be selected as outputs of the programmable timer module.

Programmable timer module coupled to microprocessor system

An integrated circuit synchronous data adaptor (SSDA) provides a bidirectional interface for synchronous data interchange. Internal control and interface logic including first-in-first-out (FIFO) buffer memory enables simultaneous transmitting and receiving of standard synchronous communication characters to allow data transfer between serial data channels and the parallel bidirectional data bus of a bus organized system such as a microprocessor (MPU) system. Parallel data from the bus system is serially transmitted and received by the SSDA with synchronization character insertion and deletion, fill character insertion and deletion, parity generation and error checking. The functional configuration of the SSDA is programmed via the MPU system data bus during system initialization and can be reconfigured via program control during subsequent system operation. Programmable control registers provide control for variable word lengths, transmit control, receive control, synchronization control, and interrupt control. Status, timing and control lines provide peripheral unit or modem control.

Synchronous serial data adaptor

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Phoenix, AZ, United States of America

Thomas C Daly