Future Wei Technologies, Inc.

Huawei Technologies Co., Limited

Boyle, Thomas

Chien, Percy

Jackson, Britt

Thomas Boyle

Guangyu Shi

Norbert Egi

Robert Lasater

John Peters

Dengke Cai

Thomas Clynne

Huisheng Zhou

Wesley M Shao

Percy Chien

Chang Yu

Ligang Chen

Britt Jackson

Qing Yi

Kevin Benner

Jian Li

Zhiyong Wang

Jianmin He

A thread on a processor core executes one or more instructions to write file data for a file into a persistent memory save area. The instructions to write the file data have the effect of storing the file data for the file in the cache associated with the processor core. The thread running on the processor core flushes the file data from the cache to the persistent memory save area while retaining the file data in the cache. The thread running on the processor core copies the file data from the cache for the processor core into a persistent copy of the file that is stored in persistent memory.

Method to consistently store large amounts of data at very high speed in persistent memory systems

A peripheral component interconnect express PCI-e network system having a processor for (a) assigning addresses to the PCI-e topology tree, comprising: traversing, at a given level and in a breadth direction, down-link couplings to an interconnection; ascertaining, at the level, which of the down-link couplings are connected to nodes; assigning, at the level, addresses to nodes of ascertained down-link coupling having nodes; and (b) propagating, a level, comprising: traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e network, ascertaining, at the level, which of the downlink couplings are coupled to other interconnections in the depth direction, consecutively proceeding in the depth direction, to a next level of the down-link coupling of a next interconnection; and alternatively repeating (a) and (b) until the nodes are assigned addresses within the PCI-e tree topology network.

Method and system for aggregation-friendly address assignment to PCIe devices

A method for accessing a device in a primary peripheral component interconnect express (PCIe) domain from a secondary PCIe domain includes determining which one or more virtual functions of the device in the primary PCIe domain are to be made available to the secondary PCIe domain. A virtual function driver is installed in the primary PCIe domain associated with the one or more virtual functions. Information corresponding to the one or more virtual functions is provided to the secondary PCIe domain. A virtual function driver associated with the one or more virtual functions is installed in the secondary PCIe domain from the information. The virtual function driver in the secondary PCIe domain has same properties as the virtual function driver in the primary PCIe domain. The device in the primary PCIe domain is accessed from the virtual function driver in the secondary PCIe domain.

Method to use PCIe device resources by using unmodified PCIe device drivers on CPUs in a PCIe fabric with commodity PCI switches

Embodiments of the present invention provide a solution for managing inter-domain resource allocation in a Peripheral Component Interconnect-Express (PCIe) network. One processor among a plurality of link processors is elected as a management processor. The management processor obtains information about available resources of PCIe network. When a resource request from a request processor is received, the management processor allocates a resource of the available resources to the requesting processor. The management processor instructs one or more link processors to program one or more inter-domain NTBs through which the traffic between the allocated resource and the requesting processor is going to flow according to the memory address information of the allocated resource, to allow cross-domain resource access between the requesting processor and the allocated resource.

Resource management for peripheral component interconnect-express domains

An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Delivering interrupts through non-transparent bridges in a PCI-express network

In a high-dimensional PCI-Express (PCIe) network, implementation of alternative paths is accomplished to facilitate flexible topology implementation and network domain scaling while enabling improved communication latency. Different portions of the PCIe tree structure are connected to allow a shorter path for communications by utilizing a bridge circuit configured as an end-point with respect to two switches that are not directly connected in the PCIe tree topology. The bridge circuit performs address translations to allow communications from one switch to be passed via the bridge circuit to the other switch.

Non-transparent bridge method and apparatus for configuring high-dimensional PCI-express networks

Method and apparatus for delivering MSI-X interrupts through non-transparent bridges to computing resources in PCI-express clusters

Growing community of inventors

Santa Clara, CA, United States of America

Thomas Boyle