Infineon Technologies Ag

Infineon Technologies Dresden Gmbh

Infineon Technologies Dresden Gmbh & Co . Kg

Thomas Bertrams

Henning Feick

Armin Tilke

Joachim Weyers

Markus Schmitt

Erhard Landgraf

Claus Dahl

Olaf Storbeck

Kerstin Kaemmer

Andreas Pribil

Matthias Schmeide

Franz Hirler

Anton Mauder

Stefan Tegen

Maik Stegemann

Sascha Weber

A power semiconductor component includes a power semiconductor partial structure having an insulating layer arranged on an upper side of a semiconductor body. A contact hole arranged on an upper side of the insulating layer proceeds from that side, extending at least partly within the insulating layer. An adhesion promoter layer arranged on an upper side of the power semiconductor partial structure at least partly covers the insulating layer upper side and a surface of the contact hole. A tungsten-comprising layer arranged on the adhesion promoter layer at least partly covers the adhesion promoter layer and has a first thickness in a region of the contact hole and dimensioned such that the tungsten-comprising layer fills the contact hole. The tungsten-comprising layer has a second thickness in the region of the insulating layer upper side which is less than the first thickness. A connection layer is arranged on the tungsten-comprising layer.

Contact hole

A method of manufacturing a semiconductor device includes forming an amorphous silicon layer over a first isolation layer. The method further includes simultaneously forming a gate oxide layer of a transistor device and transforming the amorphous silicon layer into a polycrystalline silicon layer by a thermal oxidation process. Herein a cover oxide layer is formed on the polycrystalline silicon layer.

Method of manufacturing a semiconductor device

A semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further includes a first isolation layer on the first surface of the semiconductor body and a first electrostatic discharge protection structure on the first isolation layer. The first electrostatic discharge protection structure has a first terminal and a second terminal. A second isolation layer is provided on the electrostatic discharge protection structure. A gate contact area on the second isolation layer is electrically coupled to the first terminal of the first electrostatic discharge protection structure. An electric contact structure is arranged in an overlap area between the gate contact area and the semiconductor body. The electric contact structure is electrically coupled to the second terminal of the first electrostatic discharge protection structure and electrically isolated from the gate contact area.

Semiconductor device with electrostatic discharge protection structure

According to various embodiments, a method for processing a carrier may include: doping a carrier with fluorine such that a first surface region of the carrier is fluorine doped and a second surface region of the carrier is at least one of free from the fluorine doping or less fluorine doped than the first surface region; and oxidizing the carrier to grow a first gate oxide layer from the first surface region of the carrier with a first thickness and simultaneously from the second surface region of the carrier with a second thickness different from the first thickness.

Method for processing a carrier, a carrier, and a split gate field effect transistor structure

A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in a region near the body zone and a second thickness in a region near the drift zone.

Lateral transistor component and method for producing same

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Dresden, Germany

Thomas Bertrams