Sprint Communications Comapny L.p.

Lectronix

Thomas Bayerl

Steven R Lilly

Matthew Barrow

Earl Goodrich, Ii

Craig Mahaney

Allan Dale

Brad Leedy

Christopher M Tumas

A method and system for integrating and controlling a hardware device having one or more embedded systems including one or more hardware components configurable for use with the hardware device and one or more operating systems for use with the one or more hardware components. A control module configurable for use with the one or more hardware components and one or more operating systems accesses and controls the one or more hardware components with the hardware device. The control module generates and displays access and control commands on the hardware device to allow user to operate and manage the embedded system.

Method and system for integrating and controlling components and subsystems

The present invention discloses a method of dynamically updating configuration files in a customer premises telecommunications hub. The hub includes a configuration file update module. During initialization, every system module which uses parameters in the configuration file registers with the update module. While the hub is operating, a new configuration file is sent to the IP address of the hub and written into flash memory by the update module. The update module calls a check function in the registered modules which check to see if the new parameters can be changed dynamically. If they can, the update module calls an update function in all registered modules which then change their parameters to those set by the new configuration file. If any module needs a parameter change which cannot be made dynamically, the update module calls for a system reset or reboot.

Dynamically updateable parameters in integrated services hub

The present invention discloses a method of automatically downloading and testing binary code for a customer premises telecommunications hub. When a new binary file is received by the hub, it is loaded into flash memory, but is not locked or designated as the currently active binary file. A trial run message is then written into SDRAM identifying the new file. The system if rebooted and starts up with the new file. A verification process is run to determine if the new file functions properly. If it does, the trial run message is deleted and the new file is locked into flash memory as the current binary. If the trial fails, the trial run message is deleted and the system is rebooted with the previous binary file.

Integrated services hub binary file trial run process

A method and system for extrapolating a sampling rate from received digital cells in an integrated services hub in residential or business telecommunication systems. The system is implemented by a CPU controlling the hub operations. An input buffer is implemented by the CPU and its RAM. The CPU generates a fill level indicating the relative capacity of the buffer that is filled with samples not yet coupled to a CODEC. The CPU produces a divisor based on the fill level. A baud rate generator in the CPU uses the CPU local clock and the divisor to produce a sample rate at which buffer samples are coupled to the CODEC. The divisor is adjusted to maintain the fill level within a desired range. The sample rate is also used to sample analog signals coupled to the CODEC.

Method and apparatus for synchronizing the coding and decoding of information in an integrated services hub

The present invention discloses a method and apparatus for preventing contention on a common data bus between a CPU and a peripheral device with which the CPU exchanges data. A transceiver with bus hold is used to connect the bus connections of the CPU and peripheral. Control logic receives a CPU data strobe signal and generates control signals for the transceiver and the peripheral. After these control signals go inactive, the peripheral outputs transition to the high impedance state and the bus hold circuits maintain the last peripheral output data valid for reading by the CPU at the end of its read cycle. As soon as the CPU goes to a write cycle and drives the data bus, the bus hold circuits automatically switch to follow the new data.

Use of bus hold to prevent bus contention between high speed processor and slow peripheral

The present invention discloses a method of automatically detecting and storing the CPU clock frequency in a telecommunications hub. The hub includes a known reference clock for a digital signal processor. A first counter counts the reference clock cycles during the same time period in which a second counter counts the processor clock cycles. The number of processor clock cycles counted is divided by the number of reference clock cycles counted and the result is multiplied by the frequency of the reference clock. The calculated processor clock frequency is compared to a table of available CPU clock speeds and the closest available clock speed is selected. The selected available clock speed is then stored as a variable in RAM for use by all software which uses the processor clock as a base for generating absolute timing signals, such as a one second clock.

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Williamston, MI, United States of America

Thomas Bayerl