Intel Mobile Communications Gmbh

Infineon Technologies Ag

Thomas Baumann

Christian Pacha

Stephan Henzler

Georg Georgakos

Peter Huber

Anselme Urlick Tchegho Kamgaing

Peter Mahrla

Stefan Bergler

Sascha Siegler

Gerhard Weber

Implementations are presented herein that include a plurality of on-chip monitor circuits and a controller. Each of the plurality of on-chip monitor circuits is configured to measure a parameter of a semiconductor chip. The controller is coupled to the plurality of on-chip monitor circuits. The controller is configured to receive a measurement result from at least one of the plurality of on-chip monitor circuits and to control a calibration of another one of the plurality of on-chip monitor circuits in accordance with the measurement result.

Circuit arrangement with a plurality of on-chip monitor circuits and a control circuit and corresponding methods

Implementations are presented herein that include a test circuit and a reference circuit.

Semiconductor device with a test circuit and a reference circuit

According to one aspect of this disclosure, a circuit arrangement is provided, the circuit arrangement including an electronic component coupled to at least one common power supply node and configured to provide a first signal having a variation in time that is based on power supply via the at least one common power supply node; a detecting circuit coupled to the electronic component, the detecting circuit being configured to detect the first signal and to provide a digital switch array control signal based on the variation in time of the first signal; and a switch array coupled between the at least one common power supply node and at least one power supply source, the switch array being configured to control the power supply via the at least one common power supply node based on the digital switch array control signal.

Circuit arrangement and method for operating a circuit arrangement

The present disclosure relates to on-chip self calibrating delay monitoring circuitry.

On-chip self calibrating delay monitoring circuitry

Circuit arrangement with a test circuit and a reference circuit and corresponding method

A clock control cell for production of an output clock signal from an input clock signal has a hold element and an output stage. The hold element is preceded by a signal level converter, with the signal level converter designed such that it converts an input signal to an output signal at predetermined signal levels, wherein the input clock signal is the input signal of the signal level converter.

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Anzing, Germany

Thomas Baumann