International Business Machines Corporation

Thomas Basilio Genduso

Wan Lin Leung

Donald Ingerman

Edward Robert Vanderslice

Robert Andrew Lackman

Gordon Taylor Davis

Richard Edwin Harper

Richard Allen Kelley

Shah Mohammad Rezaul Islam

Joseph M Mosley

Shauchi Ong

Harold F Kossman

Daniel J Colglazier

Chris Dombrowski

Douglas Michael Pase

Robert W Todd

Henry W Adams, Iii

A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated with the explicit request is examined to determine whether to provide one or more prefetch requests based on the prefetch attribute. Another aspect includes determining dynamic prefetch attributes for use in prefetching data, in which prefetch attributes are adjusted based on memory access requests that target next sequential blocks of memory relative to the most recent previous access in a page of memory.

Prefetch mechanism based on page table attributes

A method and system for improving the performance of a cache. The cache may include a tag entry that identifies the previously requested address by the processor whose data was not located in the cache. If the processor requests that address a second time, then there is a significant probability that the address will be accessed again. When the processor requests the address identified by the tag entry a second time, the cache is updated by inserting the data located at that address and evicting the data located in the least recently used entry. In this manner, data will not be evicted from the cache unless there is a significant probability that the data placed in the cache will likely be accessed again. Hence, data may not be evicted in the cache by the processor and replaced with data that will not be reused, such as in an interrupt routine.

Performance of a cache by including a tag that stores an indication of a previously requested address by the processor not stored in the cache

A method (and system) of improving performance of a multiprocessor system, includes proactively flushing and locking an arbitrarily-sized region of memory out of caches of the multiprocessor system.

Method and system for improving input/output performance by proactively flushing and locking an entire page out of caches of a multiprocessor system

A connection assembly comprising a receptacle portion and a probe portion. The receptacle portion is suitable for attaching to an adapter card. The receptacle may include a cylindrical housing with a longitudinal axis oriented perpendicular to the plane of the card. The receptacle includes a set of contact structures that extend within the interior of the receptacle housing. The set of contact structures are embedded within an electrically insulating contact block and preferably define one or more lines of contact structures extending perpendicularly to the plane of the adapter card. Each contact structure is electrically connected to a corresponding cable or wire. The probe portion may include a probe cover and a probe body configured to be received within the probe cover. The probe cover preferably comprises first and second elements that are separated by a gap that extends parallel to the longitudinal axis of the receptacle. The probe body includes a row of contact elements where each contact element is connected to a corresponding wire or cable. The probe body is preferably rotatable 90&#xb0; with respect to the probe cover when the probe assembly is inserted in the receptacle. The probe body may be rotatable from a first position, in which the contact elements are covered by the probe cover, to a second position, in which the contact elements are aligned with the probe cover gap(s) and further aligned with corresponding contact structures on the interior surface of the receptacle.

Connector assembly for attaching perpendicularly to an adapter card

A personal digital assistant (PDA) which includes a body portion and a keyboard adapted to be coupled to the body portion. The keyboard is a standard keyboard size when in use. The keyboard is also foldable to act as a cover for the body portion. In a preferred embodiment, the keyboard attaches directly to the PDA and when not in use acts as a cover for the display of the PDA. When the keyboard is unfolded and the PDA is placed onto a flat surface, the user is able to input information using their familiar touch-typing skills with a full-size keyboard.

Personal digital assistant including a keyboard which also acts as a cover

A cache for use in a memory controller, which processes data in a computer system having at least one processor, and a method for processing data utilizing a cache, are disclosed. The cache comprises a first array such as a tag array, a second array such as a data array, and a pointer for pointing to a portion of the second array that is associated with a portion of the first array, wherein the portion of the second array comprises the data to be processed, and wherein the number of times the at least one processor must undergo a first transfer latency is reduced. This is done by incorporating a prefetch mechanism within the cache. The computer system may include a plurality of processors with each data entry in the data array having an owner bit for each processor. The memory controller may also include a line preloader for prefetching data into the cache. Also, this design can be used in both single processor and multiprocessor systems.

Cache for processing data in a memory controller and a method of use thereof to reduce first transfer latency

A method and system in a data processing system for dynamically scheduling the processing of a plurality of requests to access a disk, in which each of the plurality of requests is associated with a location on the disk, processes the requests in a first sequential order and determines the amount of time necessary to process a selected number of requests associated with locations between the current location on the disk and the most urgent request. At a time that is earlier than the deadline for processing the most urgent request by the amount of time necessary to process the selected number of requests, the method commences processing of the selected number of requests in a second sequential order.

Method of and system for the dynamic scheduling of requests to access a storage system

A method and system in data processing system are disclosed for efficiently servicing requests to access a disk. Each of the requests are associated with a location on the disk. The requests include real-time requests and non-real time requests. A most urgent one of the requests is determined. The most urgent one of the requests is associated with a first deadline and a first location on the disk. A second most urgent one of the requests is also determined. The second most urgent one of the requests is associated with a second deadline and a second location on the disk. The first deadline is earlier in time than the second deadline. A service time is determined. The service time is earlier in time than the first deadline. The service time is determined so that sufficient time will exist to service the most urgent one of the requests before the first deadline and service the second most urgent one of the requests before the second deadline. A closest request is determined by determining whether the first location or the second location is closest to a current location of a disk arm. The closest request is either the most urgent one of the requests or the second most urgent one of the requests. In response to a current time reaching the service time, the closest request is serviced such that the most urgent one of the requests is serviced before the first deadline and the second most urgent one of the requests is serviced before the second deadline.

Data processing system and method for efficiently servicing pending requests to access a storage system

A method and system in data processing system are disclosed for the dynamic scheduling of a plurality of requests to access a disk. Each of the requests is associated with a location on the said disk which each of the requests is attempting to access. A scan queue is established for storing the plurality of requests. The plurality of requests are processed in a sequential order. The sequential order is determined utilizing the location on the disk being accessed by each of the requests. Upon one of the stored requests being urgent, the urgent request is processed. The urgent request is associated with a first location on said disk. Processing of the requests then continues in a second sequential order. The second sequential order is determined utilizing the first location. The next request to be processed is one of the requests which is associated with a physically closest location on the disk.

Method and system for the dynamic scheduling of requests to access a storage system

Bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

Snooping a variable number of cache addresses in a multiple processor system by a single snoop request

A method and system provide end-to-end flow control between a sender and a receiver attached to a network. The data is divided into a plurality of packets. A priority hierarchy of a plurality of priority levels is established. Each packet of data is associated with one of the priority levels. Transmission of the plurality of packets is initiated from a transmitter to a receiver transmitting the plurality of packets in the priority hierarchy. The real-time data is divided into a plurality of frames. Each of the plurality of frame is divided into multiple packets. Each of the plurality of frames is stored in a frame buffer included within the receiver. During transmission, a level of a plurality of frames included within the frame buffer is monitored. In response to the level crossing a first buffer threshold, a determination is made as to whether a first plurality of the multiple packets are associated with a first priority level. In response, the priority level associated with the first plurality of the multiple packets is then modified to be a second priority level. Transmission is then continued where the first plurality of the multiple packets are transmitted utilizing only the second priority level.

Method and system in a data processing system for dynamically controlling transmission of data over a network for end-to-end device flow control

A mechanism is provided for supporting stack cache memory device management of POP read or PUSH write data in a computer system. The computer system further comprises a main memory and a processor associated with the stack cache memory device. The stack cache memory device includes at least one cache line having a plurality of address spaces arranged from a lowest address to a highest address. In response to the processor initiating a POP read or PUSH write operation, the mechanism provides logic for preventing placement of data in the cache which will not be reused by the processor, and for further preventing removal of data which may be reused by the processor.

Cache memory storage space management system and method

A method and system in a superscalar data processing system are disclosed for the temporary designation and utilization of a plurality of physical registers as a stack. For each of the multiple instructions to be processed during a single clock cycle by the data processing system, a determination is made whether each of the instructions is a particular type of instruction. If a determination is made that an instruction is a particular type of instruction, a quantity of physical registers to be temporarily designated as a stack is determined utilizing the instruction. A second plurality of physical registers available to be utilized as a stack are determined whether the second plurality of the quantity. The second plurality of physical registers are then temporarily designated and utilized as a stack.

Method and system for the temporary designation and utilization of a

A memory controller having request queue and snoop tables is provided for functioning with bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The tables are compared to minimize and more efficiently institute snoop operations as a function of the presence or absence of the same listings in the tables. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

System for executing I/O request when an I/O request queue entry matches

Data is transferred over a bus from one device to another, or between one device and another system resource, such as a central processor. This data is classified into one of several types. 'Hard real time' data must be transferred within a specified time limit or 'deadline' and it is unacceptable to miss a deadline. 'Soft real time' data should be transferred before a deadline and, although some missed deadlines are tolerable, the lower the number of missed deadline the better. 'Loss sensitive' data has no deadlines, but any loss of data is unacceptable. 'Non-real time' data also has no deadlines, but the lower the time delay in transferring the data the better. The intelligence that controls the transfer of data and schedules access to the bus is distributed throughout the system. Part of this scheduling intelligence is included in the bus arbiter, while the remainder is incorporated in the devices themselves.

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Apex, NC, United States of America

Thomas Basilio Genduso