Broadlogic Network Technologies Inc.

Thomas Ayers

Weimin Zhang

Binfan Liu

Zhongqiang Wang

A system for converting digital signals in a cable network is provided. A cable head end provides a plurality of digital signals. The plurality of digital signals are grouped into a first portion and a second portion, the first portion being in a first frequency band and the second portion being in a second frequency band. The system includes a digital channel remapping module configured to select one or more digital signals from the first portion and remap the selected one or more digital signals into a first plurality of analog signals and a digital-to-analog translator configured to convert the digital signals in the second portion to a second plurality of analog signals. The first and second plurality of analog signals are combined and delivered to at least one analog device. Some or all of the second plurality of analog signals are within the first frequency band.

Method and system for providing a home cable network

A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second time basis. Sums of the timing offsets and the timing information are referred to the mapped-timing information. A correction engine is configured to update the timing offsets as timing information is encountered in the programs, and an offset register is configured to: receive the timing offsets, store the timing offsets, and transfer the timing offsets to the adder. The adder is also configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis. A program is decoder configured to receive the adjusted timestamps to decode the programs.

Method and system for multi-program clock recovery and timestamp correction

A deinterleaver for performing high-speed multi-channel forward error correction using external SDRAM is provided. According to one exemplary aspect, the deinterleaver performs both read and write accesses to the SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The data bus length of the SDRAM is designed to be twice the deinterleaving symbol size thereby allowing bandwidth to be increased. The deinterleaver accesses data in the SDRAM as read blocks and write blocks. Each block includes a predetermined number of data words to be interleaved/deinterleaved. The ACTIVE command for one block is issued when a preceding block is being processed. Data in one read/write block has the same row address within the same bank of the SDRAM.

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San Jose, CA, United States of America

Thomas Ayers