Micron Technology Incorporated

Micron Semiconductor, Inc.

Other

Thomas Arthur Figura

Li Li

Pierre C Fazan

Zhiqiang (Jeff) Wu

Kunal R Parekh

Gordon A Haller

Pai-Hung Pan

Paul J Schuele

Kevin G Donohoe

Thomas M Graettinger

Thomas Dunbar

Alan R Reinberg

Nanseng Jeng

Kin F Ma

Sujit Sharan

Ravi T Iyer

Hasan Nejad

John M Drynan

Klaus Florian Schuegraf

John Mark Meldrim

Bradley J Howard

Zhiquiang Wu

Justin Harnish

Gurtej S Sandhu

Trung Tri Doan

Howard E Rhodes

Fernando N Gonzalez

Werner Juengling

J Brett Rolfson

Kevin R Shea

Anand Srinivasan

Brett W Busch

Marsela Pontoh

Steven D Cummings

Kirk D Prall

John K Zahurak

Fatma Arzum Simsek-Ege

Xiao Li

Viju K Mathews

Anish A Khandekar

Scott L Light

Sanjeev Sapra

Shane J Trapp

Jeffery B Hull

Hung-Wei Liu

Zhiqiang Xie

Song Guo

Shen Hu

Angus C Fox, Iii

Zhigiang (Jeff) Wu

Kangle Li

Yan Li

Yashvi Singh

Siva Naga Sandeep Chalamalasetty

Corey Staller

Vivek Yadav

Stephen D Snyder

Ping Chieh Chiang

A microelectronic device comprises memory cell structures extending from a base material. At least one memory cell structure of the memory cell structures comprises a central portion in contact with a digit line, extending from the base material and comprising opposing arcuate surfaces, an end portion in contact with a storage node contact on a side of the central portion, and an additional end portion in contact with an additional storage node contact on an opposite side of the central portion. Related microelectronic devices, electronic systems, and methods are also described.

Microelectronic devices including memory cell structures, and related methods and electronic systems

An example apparatus includes forming a working surface of a substrate material. The example apparatus includes trench formed between two semiconductor structures on the working surface of the substrate material. The example apparatus further includes access lines formed on neighboring sidewalls of the semiconductor structures opposing a channel region separating a first source/drain region and a second source/drain region. The example apparatus further includes a time-control formed inhibitor material formed over a portion of the sidewalls of the semiconductor structures. The example apparatus further includes a dielectric material formed over the semiconductor structures to enclose a non-solid space between the access lines.

Semiconductor structure formation

Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.

Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.

Silicided recessed silicon

Semiconductor device structures include an at least partially formed container capacitor having a generally cylindrical first conductive member with at least one inner sidewall surface, a lattice material at least partially laterally surrounding an upper end portion of the first conductive member, an anchor material, and at least one aperture extending through the lattice material between the at least partially formed container capacitor and an adjacent at least partially formed container capacitor. Other structures include an at least partially formed container capacitor, a lattice material, and an anchor material disposed over a surface of the lattice material and at least a portion of an end surface of the first conductive member and forming a chemical barrier over at least a portion of an interface between the lattice material and the upper end portion of the first conductive member.

Semiconductor devices and structures including at least partially formed container capacitors

Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.

Peripheral gate stacks and recessed array gates

Methods of forming semiconductor devices that include one or more container capacitors include anchoring an end of a conductive member to a surrounding lattice material using an anchor material, which may be a dielectric. The anchor material may extend over at least a portion of an end surface of the conductive member, at least a portion of the lattice material, and an interface between the conductive member and the lattice material. In some embodiments, the anchor material may be formed without significantly covering an inner sidewall surface of the conductive member. Furthermore, in some embodiments, a barrier material may be provided over at least a portion of the anchor material and over at least a portion of an inner sidewall surface of the conductive member. Novel semiconductor devices and structures are fabricated using such methods.

Semiconductor devices and structures including at least partially formed container capacitors and methods of forming the same

Method of forming a transistor gate of a recessed access device, method of forming a recessed transistor gate and a non-recessed transistor gate, and method of fabricating an integrated circuit

A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Use of a plasma source to form a layer during the formation of a semiconductor device

A method for forming a double sided container capacitor comprises forming a first capacitor top plate layer within a recess in a dielectric layer, then forming a first cell dielectric on the first top plate layer. Next, first and second bottom plate layers are formed on the first cell dielectric layer, and a second cell dielectric layer is formed on the second bottom plate layers. Finally, a second top plate layer is formed on the second cell dielectric layer, and the first and second top plate layers are electrically connected using a conductive plug or conductive spacer. An inventive structure formed using the inventive method is also described.

Double sided container capacitor for a semiconductor device

This invention includes methods of forming openings into dielectric material. In one implementation, an opening is partially etched through dielectric material, with such opening comprising a lowest point and opposing sidewalls of the dielectric material. At least respective portions of the opposing sidewalls within the opening are lined with an electrically conductive material. With such electrically conductive material over said respective portions within the opening, plasma etching is conducted into and through the lowest point of the dielectric material of the opening to extend the opening deeper within the dielectric material. Other aspects and implementations are contemplated.

Methods of forming openings into dielectric material

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Boise, ID, United States of America

Thomas Arthur Figura