International Business Machines Corporation

Globalfoundries Inc.

Siemens Aktiengesellschaft

Thomas Anthony Wassick

Charles Leon Arvin

Arthur Gilman Merryman

Krystyna Waleria Semkow

Roy Rongqing Yu

Eric D Perfecto

Wolfgang Sauter

Jon Alfred Casey

Timothy Harrison Daubenspeck

Timothy Dooling Sullivan

David L Questad

Shidong Li

Christopher David Muzzy

Thomas M Shaw

Krishna R Tunga

Brian Richard Sundlof

Ian D Melville

David Clifford Long

Gerald Keith Bartley

Minhua Lu

Sushumna Iruvanti

Steven Lorenz Wright

Mark J LaPlante

Mario John Interrante

Robert Anthony Rita

Donald Rene Wall

Richard Francis Indyk

Suryanarayana Kaja

Glenn A Pomerantz

James G Balz

Ekta Misra

Kimberley A Kelly

Michael Berger

Charles J Hendricks

Kurt A Smith

Richard Philip Surprenant

Kamalesh S Desai

Kirk David Peterson

Thomas Weiss

Raschid Jose Bezama

Jeffrey Allen Zitz

James Gardner Ryan

Sudipta Kumar Ray

Steven Paul Ostrander

Peter Jeffrey Brofman

Chandrika Prasad

Harry David Cox

Xiaojin Wei

Raymond A Jackson

Rajesh S Patel

Brian W Quinlan

William Edward Sablinski

Tuhin Sinha

Robin A Susko

Raj N Master

Steve Ostrander

Bhupender Singh

Randall Jason Werner

Alexander R Mitwalsky

Jeffrey P Gambino

Thomas H Baum

Paul Stephen Andry

Bucknell Chapman Webb

Karthick Rajamani

Russell Alan Budd

Laertis Economikos

Xiao Hu Liu

Peilin Song

David John Russell

Charles Robert Lefurgy

Franco Stellari

Krishna Gandhi Sachdev

Malcolm Scott Allen-Ware

James A Busby

Sung Kwon Kang

Michael Jay Shapiro

Alan J Drake

William Santiago-Fernandez

Mark C H Lamorey

Paul B Comita

Sungjun Chun

Victor V Zyuban

Thomas Edward Lombardi

Brian Michael Erwin

Madhavan Swaminathan

Michael F McAllister

Nihad Hadzic

Mukta S Farooq

Luc Gilbert Guerin

George E White

Leena Paivikki Buchwalter

Sylvain E Ouimet

Srinivasa S N Reddy

Jeonghee Shin

Jeffrey Scott Zimmerman

Robert L Jackson

Chung-Ching Lin

Gregg B Monjeau

Charles C Goldsmith

Ashwani K Malhotra

A laminate carrier-like module lid including multiple laminate layers of non-conductive materials stacked one atop another, sensor circuitry embedded within the laminate carrier-like module lid, the sensor circuitry providing a continuous electrical circuit surrounding the electronic components of the multi-chip module package, and thermal circuitry embedded within the laminate carrier-like module lid, the thermal circuitry comprising solid copper traces to thermally conduct heat from the electronic components of the multi-chip module package.

Multi chip hardware security module

A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

High bandwidth module

Rework and recovery processes generally include application of liquid metal etchant compositions to selectively remove one layer at a time of a solder layer and underball metallurgy multilayer stack including a titanium-based adhesion layer, a copper seed layer, a plated copper conductor layer, and a nickel-based barrier layer. The rework and recovery process can be applied to the dies, wafers, and/or substrate.

Flip chip packaging rework

A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.

Lead-free solder joining of electronic structures

Multiple integrated circuit (IC) devices are connected to a top side metallization surface of a multi IC device carrier. The carrier includes resin based substrate layers and associated wiring line layers. To reduce stain of the resin layers, especially in region(s) within the carrier between the IC devices, a stiffener or stiffeners are applied to the back side metallization (BSM) surface of the IC device carrier. The stiffener(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the resin layer(s), thereby mitigating the risk for cracks forming and expanding within the resin layers.

Mitigating cracking within integrated circuit (IC) device carrier

A semiconductor device that includes a substrate having integrated circuits; a plurality of metallization layers on the substrate, the plurality of metallization layers having a peripheral region adjacent to a kerf region of the semiconductor device and containing a crack stop structure extending through the plurality of metallization layers; a trench extending through the plurality of metallization layers and adjacent to the crack stop structure, the trench filled with a material that creates compressive stresses between the filled trench and the adjacent metallization layers to form a compressive zone adjacent to the crack stop structure. Also disclosed is a method for forming the semiconductor device.

Compressive zone to reduce dicing defects

Place a first semiconductor chip onto an alignment carrier with protrusions of the semiconductor chip inserted into corresponding cavities of the alignment carrier, so that the protrusions and cavities locate the semiconductor chip with interconnect contacts overlying a window that is formed through the alignment carrier. Place a second semiconductor chip onto the alignment carrier with protrusions of the second semiconductor chip inserted into cavities of the alignment carrier, so that the protrusions and cavities locate the second semiconductor chip with interconnect contacts of the second semiconductor chip adjacent to the interconnect contacts of the first semiconductor chip and overlying the window. Fasten the semiconductor chips to the alignment carrier. Touch contacts of a interconnect bridge against the interconnect contacts of the first and second semiconductor chips by putting the interconnect bridge through the window.

Precision alignment of multi-chip high density interconnects

Techniques that facilitate integrated circuit defect detection using pattern images are provided. In one example, a system generates an equalized pattern image of a pattern image associated with a module under test based on an adaptive contrast equalization technique. The system also identifies a first set of features of the equalized pattern image based on a feature point detection technique and aligns the equalized pattern image with a reference pattern image based on the first set of features and a second set of features of the reference pattern image. Furthermore, the system compares a first set of light intensities of the equalized pattern image to a second set of light intensities of the reference pattern image to identify one or more regions of the module under test that satisfy a defined criterion associated with a defect for the module under test.

Integrated circuit defect detection using pattern images

A semiconductor device which includes a substrate having integrated circuits; and metallization layers on the substrate, the metallization layers having a peripheral region adjacent to a kerf region of the semiconductor device and containing a crack stop structure. The crack stop structure includes a bottom portion containing a plurality of the metallization layers connected by vias with each metallization layer decreasing in width in a step pyramid structure from a bottom of the bottom portion to a top of the bottom portion; and a top portion containing a top metallization layer of the metallization layers connected to the bottom portion, the top metallization layer being wider than a top-most metallization layer of the bottom portion and having a segment that extends toward the kerf region so as to create an overhang with respect to the bottom portion.

Step pyramid shaped structure to reduce dicing defects

A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.

Test cell for laminate and method

A methodology and associated wafer level assembly of testing crackstop structure designs. The wafer level semiconductor assembly includes: a substrate structure shaped to define a set of horizontal directions; a metallization layer located on top of the substrate structure, with the metallization layer including a crackstop structure formed therein in accordance with a crackstop structure design; and a tensioned layer located on top of the metallization layer, with the tensioned layer being made of material having internal tensile forces oriented in the horizontal directions. The tensile forces promote horizontal direction crack propagation in the metallization layer so that the crackstop structure design can be tested more rigorously and reliably before deciding on the crackstop design structure to put into mass production (which mass produced product would typically not include the tensioned layer).

Determining crackstop strength of integrated circuit assembly at the wafer level

A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.

Semiconductor device contact structure having stacked nickel, copper, and tin layers

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Lagrangeville, NY, United States of America

Thomas Anthony Wassick